M38504M6-SS Просмотр технического описания (PDF) - Renesas Electronics

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M38504M6-SS

8-BIT CISC SINGLE-CHIP MICROCOMPUTER

Renesas Electronics 

List of figures

Fig. 2.4.28 Control procedure of Serial I/O1 ............................................................................ 2-58

Fig. 2.4.29 Registers setting relevant to Serial I/O2 .............................................................. 2-59

Fig. 2.4.30 Setting of serial I/O2 transmission data ............................................................... 2-59

Fig. 2.4.31 Control procedure of Serial I/O2 ............................................................................ 2-60

Fig. 2.4.32 Connection diagram ................................................................................................. 2-61

Fig. 2.4.33 Timing chart .............................................................................................................. 2-62

Fig. 2.4.34 Relevant registers setting ....................................................................................... 2-62

Fig. 2.4.35 Control procedure of master unit ........................................................................... 2-63

Fig. 2.4.36 Control procedure of slave unit ............................................................................. 2-64

Fig. 2.4.37 Connection diagram ................................................................................................. 2-65

Fig. 2.4.38 Timing chart (using UART) ..................................................................................... 2-65

Fig. 2.4.39 Registers setting relevant to transmitting side ..................................................... 2-67

Fig. 2.4.40 Registers setting relevant to receiving side ......................................................... 2-68

Fig. 2.4.41 Control procedure of transmitting side .................................................................. 2-69

Fig. 2.4.42 Control procedure of receiving side ...................................................................... 2-70

Fig. 2.4.43 Sequence of setting serial I/O1 control register again ....................................... 2-72

Fig. 2.5.1 Memory map of registers relevant to PWM ........................................................... 2-74

Fig. 2.5.2 Structure of PWM control register ........................................................................... 2-74

Fig. 2.5.3 Structure of PWM prescaler ..................................................................................... 2-75

Fig. 2.5.4 Structure of PWM register ........................................................................................ 2-75

Fig. 2.5.5 Connection diagram ................................................................................................... 2-76

Fig. 2.5.6 PWM output timing ..................................................................................................... 2-76

Fig. 2.5.7 Setting of relevant registers ..................................................................................... 2-77

Fig. 2.5.8 PWM output ................................................................................................................ 2-77

Fig. 2.5.9 Control procedure ....................................................................................................... 2-78

Fig. 2.6.1 Memory map of registers relevant to A-D converter ............................................ 2-79

Fig. 2.6.2 Structure of A-D control register .............................................................................. 2-79

Fig. 2.6.3 Structure of A-D conversion register (high-order) ................................................. 2-80

Fig. 2.6.4 Structure of A-D conversion register (low-order) ................................................... 2-80

Fig. 2.6.5 Structure of Interrupt request register 2 ................................................................. 2-81

Fig. 2.6.6 Structure of Interrupt control register 2 .................................................................. 2-81

Fig. 2.6.7 Connection diagram ................................................................................................... 2-82

Fig. 2.6.8 Relevant registers setting ......................................................................................... 2-82

Fig. 2.6.9 Control procedure for 8-bit read .............................................................................. 2-83

Fig. 2.6.10 Control procedure for 10-bit read .......................................................................... 2-83

Fig. 2.7.1 Memory map of registers relevant to watchdog timer .......................................... 2-85

Fig. 2.7.2 Structure of Watchdog timer control register ......................................................... 2-85

Fig. 2.7.3 Structure of CPU mode register .............................................................................. 2-86

Fig. 2.7.4 Watchdog timer connection and division ratio setting .......................................... 2-87

Fig. 2.7.5 Relevant registers setting ......................................................................................... 2-88

Fig. 2.7.6 Control procedure ....................................................................................................... 2-88

Fig. 2.8.1 Example of poweron reset circuit ............................................................................ 2-89

Fig. 2.8.2 RAM backup system .................................................................................................. 2-89

Fig. 2.9.1 Structure of CPU mode register .............................................................................. 2-91

Fig. 2.9.2 Connection diagram ................................................................................................... 2-92

Fig. 2.9.3 Status transition diagram during power failure ...................................................... 2-92

Fig. 2.9.4 Setting of relevant registers ..................................................................................... 2-93

Fig. 2.9.5 Control procedure ....................................................................................................... 2-94

Fig. 2.10.1 Structure of MISRG ................................................................................................. 2-95

Fig. 2.10.2 Oscillation stabilizing time at restoration by reset input .................................... 2-97

Fig. 2.10.3 Execution sequence example at restoration by occurrence of INT0 interrupt request

........................................................................................................................................................ 2-99

3850 Group (Spec. H) User’s Manual

vii

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