M38504M6-FP Просмотр технического описания (PDF) - Renesas Electronics

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M38504M6-FP

8-BIT CISC SINGLE-CHIP MICROCOMPUTER

Renesas Electronics 

List of figures

List of figures

CHAPTER 1 HARDWARE

Fig. 1 M38503MXH-XXXFP/SP pin configuration ...................................................................... 1-2

Fig. 2 Functional block diagram ................................................................................................... 1-3

Fig. 3 Part numbering .................................................................................................................... 1-5

Fig. 4 Memory expansion plan ..................................................................................................... 1-6

Fig. 5 740 Family CPU register structure ................................................................................... 1-8

Fig. 6 Register push and pop at interrupt generation and subroutine call ........................... 1-9

Fig. 7 Structure of CPU mode register ..................................................................................... 1-11

Fig. 8 Memory map diagram ...................................................................................................... 1-12

Fig. 9 Memory map of special function register (SFR) .......................................................... 1-13

Fig. 10 Port block diagram (1) ................................................................................................... 1-15

Fig. 11 Port block diagram (2) ................................................................................................... 1-16

Fig. 12 Port block diagram (3) ................................................................................................... 1-17

Fig. 13 Interrupt control ............................................................................................................... 1-20

Fig. 14 Structure of interrupt-related registers ......................................................................... 1-20

Fig. 15 Structure of timer XY mode register ............................................................................ 1-21

Fig. 16 Structure of timer count source selection register ..................................................... 1-21

Fig. 17 Block diagram of timer X, timer Y, timer 1, and timer 2 ......................................... 1-22

Fig. 18 Block diagram of clock synchronous serial I/O1 ........................................................ 1-23

Fig. 19 Operation of clock synchronous serial I/O1 function ................................................ 1-23

Fig. 20 Block diagram of UART serial I/O1 ............................................................................. 1-24

Fig. 21 Operation of UART serial I/O1 function ...................................................................... 1-25

Fig. 22 Structure of serial I/O1 control registers ..................................................................... 1-26

Fig. 23 Structure of serial I/O2 control registers 1, 2 ............................................................ 1-27

Fig. 24 Block diagram of serial I/O2 ......................................................................................... 1-28

Fig. 25 Timing chart of serial I/O2 ............................................................................................ 1-28

Fig. 26 SCMP2 output operation ................................................................................................... 1-29

Fig. 27 Timing of PWM period ................................................................................................... 1-30

Fig. 28 Block diagram of PWM function ................................................................................... 1-30

Fig. 29 Structure of PWM control register ............................................................................... 1-31

Fig. 30 PWM output timing when PWM register or PWM prescaler is changed ................ 1-31

Fig. 31 Structure of AD control register ................................................................................... 1-32

Fig. 32 Structure of A-D conversion registers ......................................................................... 1-32

Fig. 33 Block diagram of A-D converter ................................................................................... 1-32

Fig. 34 Block diagram of Watchdog timer ................................................................................ 1-33

Fig. 35 Structure of Watchdog timer control register ............................................................. 1-33

Fig. 36 Reset circuit example .................................................................................................... 1-34

Fig. 37 Reset sequence .............................................................................................................. 1-34

Fig. 38 Internal status at reset .................................................................................................. 1-35

Fig. 39 Ceramic resonator circuit .............................................................................................. 1-36

Fig. 40 External clock input circuit ............................................................................................ 1-36

Fig. 41 Structure of MISRG ........................................................................................................ 1-37

Fig. 42 System clock generating circuit block diagram (Single-chip mode) ........................ 1-37

Fig. 43 State transitions of system clock ................................................................................. 1-38

Fig. 44 Block diagram of flash memory version ...................................................................... 1-40

Fig. 45 Flash memory control registers .................................................................................... 1-42

iv

3850 Group (Spec. H) User’s Manual

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