M25PE16 Просмотр технического описания (PDF) - STMicroelectronics

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M25PE16

16 Mbit, low-voltage, Page-Erasable Serial Flash memory with byte-alterability, 50 MHz SPI bus, standard pinout

STMicroelectronics 

Signal description

2

Signal description

M25PE16

2.1

Serial Data Output (Q)

This output signal is used to transfer data serially out of the device. Data is shifted out on the

falling edge of Serial Clock (C).

2.2

Serial Data Input (D)

This input signal is used to transfer data serially into the device. It receives instructions,

addresses, and the data to be programmed. Values are latched on the rising edge of Serial

Clock (C).

2.3

Serial Clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data

present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on

Serial Data Output (Q) changes after the falling edge of Serial Clock (C).

2.4

Chip Select (S)

When this input signal is High, the device is deselected and Serial Data Output (Q) is at high

impedance. Unless an internal Read, Program, Erase or Write cycle is in progress, the

device will be in the Standby mode (this is not the Deep Power-down mode). Driving Chip

Select (S) Low selects the device, placing it in the Active Power mode.

After Power-up, a falling edge on Chip Select (S) is required prior to the start of any

instruction.

2.5

Reset (RESET)

The Reset (RESET) input provides a hardware reset for the memory.

When Reset (RESET) is driven High, the memory is in the normal operating mode. When

Reset (RESET) is driven Low, the memory will enter the Reset mode. In this mode, the

output is high impedance.

Driving Reset (RESET) Low while an internal operation is in progress will affect this

operation (write, program or erase cycle) and data may be lost.

See Table 12 for the status of the device after a RESET Low pulse.

2.6

Write Protect (W)

The Write Protect (W) input is used to freeze the size of the area of memory that is

protected against write, program and erase instructions (as specified by the values in the

BP2, BP1 and BP0 bits of the Status Register). See Section 6.4: Read Status Register

(RDSR).

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