MT8960AE Просмотр технического описания (PDF) - Zarlink Semiconductor Inc

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MT8960AE

Integrated PCM Filter Codec

Zarlink Semiconductor Inc 

MT8960/61/62/63/64/65/66/67

Data Sheet

AC Electrical Characteristics - Receive (D/A) Path - Voltages are with respect to GNDD unless otherwise stated.

TA=0 to 70°C, VDD=5V±5%, VEE=-5V±5%, VRef=2.5V±0.5%, GNDA=GNDD=0V, Clock Frequency = 2.048MHz,

Filter Gain Setting = 0dB. Outputs unloaded unless otherwise specified.

11

Envelope Delay

DAR

12

Envelope Delay 1000-2600 Hz DDR

Variation with 600-3000 Hz

Frequency

400-3200 Hz

210

90

170

265

µs @ 1004 Hz

µs Input Signal:

µs 400 - 3200 Hz digital

µs sinewave at 0 dBm0

13

Gain Relative to <200 Hz

Gain @ 1004 Hz 200 Hz

A (See Figure 11) 300-3000 Hz

N

3300 Hz

A

3400 Hz

L

4000 Hz

O

≥4600 Hz

G

14

Crosstalk A/D to D/A

GRR

CTTR

-0.5

-0.125

-0.350

-0.80

0.125

0.125

0.125

0.030

-0.100

-14.0

-28.0

-70

dB 0 dBm0 Input Signal

dB

dB Receive

dB Filter

dB Response

dB

dB

dB 0 dBm0 @ 1.02 kHz

in A/D

15

Power Supply

Rejection

VDD

PSRR3 33

VEE

PSRR4 35

dB Input 50 mVRMS at

dB 1.02 kHz

16

Overload Distortion

Input frequency=1.02

(See Fig. 15)

kHz

* Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing.

Note 7: 0dBm0=1.185 VRMS for µ-Law codec and 0dBm0=1.231 VRMS for A-Law codec.

20

Zarlink Semiconductor Inc.

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