CXD1913AQ Просмотр технического описания (PDF) - Sony Semiconductor

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производитель

CXD1913AQ

Digital Video Encoder

Sony Semiconductor 

CXD1913AQ

Pin

No.

Symbol I/O

Description

32 C-OUT

O 10-bit D/A converter output. This pin outputs chroma (C) signal.

33 TD10

Test data bus.

This pin should be open.

I/O For test mode, it’s used for internal circuit test data bus.

Test mode is available only for device bender.

34 VDD

— Digital power supply

35 TD9

36 TD8

I/O Test data bus.

These pins should be open.

For test mode, it’s used for internal circuit test data bus.

I/O Test mode is available only for device bender.

37 XTEST1

38 XTEST2

39 XTEST3

I

Test mode control inputs. These pins are pulled up.

I Normally, these pins should be open.

I

40 VSS

— Digital ground

41 TRST

Test mode reset input. This pin is pulled up.

I For power on reset, set “L” for more than 40 clocks (SYSCLK).

42 VDD

— Digital power supply

43 TDI

I Test mode control input. This pin is pulled up.

44 TMS

I Test mode control input. This pin is pulled up.

45 TCK

I Test mode control input. This pin should be “H” input.

46 TDO

O Test data bus output. This pin should be open.

47 VSS

— Digital ground

48 SI/SDA

This pin's function is selected by XIICEN (Pin 64).

I When XIICEN = “H”, this pin is SONY SIO mode; SI serial data input.

When XIICEN = “L”, this pin is I2C bus mode; SDA input/output.

49 SCK/SCL

This pin's function is selected by XIICEN (Pin 64).

I When XIICEN = “H”, this pin is SONY SIO mode; SCK serial clock input.

When XIICEN = “L”, this pin is I2C bus mode; SCL input.

50 XCS/SA

This pin's function is selected by XIICEN (Pin 64). This pin is pulled up.

When XIICEN = “H”, this pin is SONY SIO mode; XCS chip select input.

I When XIICEN = “L”, this pin is I2C bus mode; SA slave address select input

signal which selects I2C bus slave address.

51 XVRST

Vertical sync reset input in active low. This pin is pulled up.

This is used to synchronize external vertical sync and internal vertical sync.

I When XVRST is “L”, internal digital sync generator is reset according to F1 status.

Valid only for 8-bit mode (control register address 01H bit 4 "PF MODE" = "0").

52

F1/

XTEST4

This pin's function is selected by XTEST (Pin 54).

When XTEST = "H", this pin is F1; field ID input.

I

Field ID during vertical sync reset is indicated.

“H” indicates 1st field. “L” indicates 2nd field.

When XTEST = "L", XTEST4 input.

–4–

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