CXD1913AQ
Item
SYSCLK clock rate
SYSCLK pulse width Low
SYSCLK pulse width High
PDCLK delay time from SYSCLK
Control output delay time from SYSCLK
Control output hold time from SYSCLK
(Ta = 0 to +70°C, VDD = 3.3V ± 5%, Vss = 0V)
Symbol
fSYSCLK
tPWLCLK
tPWHCLK
tPDCLKD ∗
tCOD ∗
tCOH ∗
Min.
11
11
3
Typ.
27
Max. Unit
MHz
ns
ns
23
ns
25
ns
ns
∗ CL = 35pF
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