CXD1913AQ
3. XVRST, F1
SYSCLK
XVRST
F1
Item
XVRST setup time to SYSCLK
XVRST hold time to SYSCLK
tVS
tVH
(Ta = 0 to +70°C, VDD = 3.3V ± 5%, 5.0V ± 5%, Vss = 0V)
Symbol Min.
tVS
20
tVH
0
Typ.
Max. Unit
ns
ns
4. SYSCLK, PDCLK, VSYNC, HSYNC, FID
SYSCLK
fSYSCLK
tPWHCLK
tPWLCLK
PDCLK
VSYNC,
HSYNC,
FID
tPDCLKD
tCOD
tCOH
tPDCLKD
Item
SYSCLK clock rate
SYSCLK pulse width Low
SYSCLK pulse width High
PDCLK delay time from SYSCLK
Control output delay time from SYSCLK
Control output hold time from SYSCLK
(Ta = 0 to +70°C, VDD = 5.0V ± 5%, Vss = 0V)
Symbol
fSYSCLK
tPWLCLK
tPWHCLK
tPDCLKD ∗
tCOD ∗
tCOH ∗
Min.
11
11
3
Typ.
27
Max. Unit
MHz
ns
ns
15
ns
20
ns
ns
∗ CL = 35pF
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