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TEA1751LT

HV start-up DCM/QR flyback controller with integrated DCM/QR PFC controller

NXP Semiconductors. 

NXP Semiconductors

TEA1751LT

HV start-up flyback controller with integrated PFC controller

7.1.4 Fast latch reset

In a typical application, the mains can be interrupted briefly to reset the latched protection.

The PFC bus capacitor, Cbus, does not have to discharge for this latched protection to

reset.

When the VINSENSE voltage drops below 750 mV and is then raised to 870 mV, the

latched protection is reset.

The latched protection is also reset by removing the voltage from the VCC and HV pins.

7.1.5 Overtemperature protection

An accurate internal temperature protection is provided in the circuit. When the junction

temperature exceeds the thermal shut-down temperature, the IC stops switching. As long

as OTP is active, the capacitor CVCC is not recharged from the HV mains. If the VCC

supply voltage is not sufficient, the OTP circuit is supplied from the HV pin.

OTP is a latched protection. It is reset by removing the voltage from the VCC and HV pins

or by the fast latch reset function (see Section 7.1.4).

7.2 Power factor correction circuit

The power factor correction circuit operates in quasi-resonant or Discontinuous

Conduction Mode (DCM) with valley switching. The next primary stroke is only started

when the previous secondary stroke has ended and the voltage across the PFC MOSFET

has reached a minimum value. VPFCAUX is used to detect transformer demagnetization

and the minimum voltage across the external PFC MOSFET switch.

7.2.1 ton control

The power factor correction circuit is operated in ton control. The resulting mains harmonic

reduction is well within the class-D requirements.

7.2.2 Valley switching and demagnetization (PFCAUX pin)

The PFC MOSFET is switched on after the transformer is demagnetized. Internal circuitry

connected to the PFCAUX pin detects the end of the secondary stroke. It also detects the

voltage across the PFC MOSFET. To reduce switching losses and electromagnetic

Interference (EMI) (valley switching), the next stroke is started if the voltage across the

PFC MOSFET is at its minimum.

If a demagnetization signal is not detected on the PFCAUX pin, the controller generates a

Zero-current Signal (ZCS), 50 s after the last PFCGATE signal.

If a valley signal is not detected on the PFCAUX pin, the controller generates a valley

signal 4 s after demagnetization is detected.

To protect the internal circuitry during lightning events, for example, add a 5 k series

resistor to PFCAUX. To prevent incorrect switching due to external disturbance, place the

resistor close to the IC on the printed-circuit board.

TEA1751LT

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 3. — 9 January 2013

© NXP B.V. 2013. All rights reserved.

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