AD9684 Просмотр технического описания (PDF) - Analog Devices

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AD9684

14-Bit, 500 MSPS LVDS, Dual Analog-to-Digital Converter

Analog Devices 

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AD9684

VIN±x

APERTURE DELAY

N

N+x

N + 36

N + 37

N + 38

SYNC+

SYNC–

CLK+

CLK–

DCO± (DATA CLOCK OUTPUT)

0° PHASE ADJUST

SYNCHRONOUS LOW TO HIGH TRANSITIONS OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF

THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET

CONSTANT LATENCY = X CLK CYCLES

tDCO

tPD

tCLK

DCO± (DATA CLOCK OUTPUT)

180° PHASE ADJUST

STATUS BIT SELECTED BY

REGISTER 0x559, BITS[2:0]

IN THE REGISTER MAP

STATUS+

(OVERRANGE/STAUS BIT)

STATUS–

STATUS STATUS

tSKEWR

tSKEWF

CONVERTERS

SAMPLE

[N]

CONVERTERS

SAMPLE

[N]

CONVERTERS

SAMPLE

[N + 1]

CONVERTERS

SAMPLE

[N + 1]

CONVERTERS

SAMPLE

[N + 2]

STATUS STATUS STATUS STATUS STATUS STATUS

CHANNEL A D12±/D13±

CHANNEL A D0±/D1±

S[N – y]

S[N – x]

(ODD BITS) (EVEN BITS)

S[N – 1]

S[N]

S[N]

S[N + 1]

S[N + 1]

S[N + 2]

(ODD BITS) (EVEN BITS) (ODD BITS) (EVEN BITS) (ODD BITS) (EVEN BITS)

Figure 6. Channel Multiplexed (Even/Odd) Mode—One Converter, ≤14-Bit Data

Rev. 0 | Page 11 of 64

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