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Note
1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions: RL (connects to VCC): 1.3 k (2.5V, 5V), 10 k (1.8V)
Input pulse voltages: 0.3 VCC to 0.7 VCC
Input rise and fall time: 50 ns
Input and output timing reference voltages: 0.5 VCC
The value of RL should be concerned according to the actual loading on the user's system.
Bus Timing
Figure 10: SCL: Serial Clock, SDA: Serial Data I/O
Write Cycle Timing
Figure 11: SCL: Serial Clock, SDA: Serial Data I/O
Note
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the
internal clear/write cycle.
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