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QN8075

Single Chip Low Power FM Receiver for Portable Devices

Unspecified 

4 Control Interface Protocol

The QN8075 supports the standard I2C serial interfaces.

At power-on, all register bits are set to default values.

I2C Serial Control Interface

QN8075 provides an I2C-compatible serial interface. It

consists of two wires; serial bi-directional data line

(SDA) and input clock line (SCL). It operates as a slave

on the bus and the slave address is 0010000. The data

transfer rate on the bus is up to 400 Kbit/s.

SDA must be stable during the high period of SCL,

except for start and stop conditions. SDA can only

change with SCL being low. A high-to-low transition on

SDA while SCL is high indicates a start condition. A

low-to-high transition on SDA while SCL is high

indicates a stop condition.

An I2C master initiates a data transfer by generating a

start condition followed by the QN8075 slave address,

MSB first, followed by a 0 to indicate a write cycle.

After receiving an ACK from the QN8075 (by pulling

SDA low), the master sends the sub-address of the

register, or the first of a block of registers it wants to

write, followed by one or more bytes of data, MSB first.

The QN8075 acknowledges each byte after completion

of each transfer. The I2C master terminates the write

operation by generating a stop condition (P).

The read operation consists of two phases. The first

phase is the address phase. In this phase, an I2C master

initiates a write operation to the QN8075 by generating a

start condition (S) followed by the QN8075 slave address,

MSB first, followed by a 0 to indicate a write cycle.

After receiving ACK from the QN8075, the master sends

the sub-address of the register or the first of a block of

registers it wants to read. After the cycle is

acknowledged, the master terminates the cycle

immediately by generating a stop condition (P).

The second phase is the data phase. In this phase, an I2C

master initiates a read operation to the QN8075 by

generating a start condition followed by the QN8075

slave address, MSB first, followed by a 1 to indicate a

read cycle. After an acknowledge from the QN8075, the

I2C master receives one or more bytes of data from the

QN8075. The I2C master acknowledges the transfer at the

end of each byte. After the last data byte to be sent has

been transferred from the QN8075 to the master, the

master generates a NACK followed by a stop.

The timing diagrams below illustrate both write and read operations.

Notes:

1.

2.

Figure 6 I2C Serial Control Interface Protocol

The default IC address is 0010000.

“20” for a WRITE operation, “21” for a READ operation.

Rev 0.2c (09/02)

Copyright ©2011 by Quintic Corporation

Page 12

Confidential A

Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).

Advance Technical Information. This is a product under development. Characteristics and specifications are subject to change without notice.

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