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ML2721

Low IF Digital Cordless Transceiver

Micro Linear Corporation 

PRELIMINARY

ML2721

PIN DESCRIPTIONS (continued)

Pin # Signal Name

I/O

Description

Power & Ground (Continued)

29

RVCC7

O (analog)

25

GND

I (analog)

12

GND

I (analog)

17

GND

I (analog)

18

GND

I (analog)

19

GND

I (analog)

20

GND

I (analog)

31

VDD

I (analog)

8

VSS

Transmit/Receive

21

RRFI

23

TRFO

Data

30

DIN

I (digital)

I (analog)

O (analog)

I (CMOS)

32

DOUT

O (CMOS)

Mode Control and Interface Lines

1

XCEN

I (CMOS)

2

RXON

I (CMOS)

DC power supply decoupling point for IF, Demodulator, and Data

Slicer circuits. There must be a capacitor to ground from this pin to

decouple (bypass) noise and to stabilize the regulator

DC Ground to IF, Demodulator, and Data Slicer circuits

Ground for the PLL dividers, phase detector, and charge pump

Signal ground for RF small signal circuits. Pins 17, 18, and 19 should

have short, direct connections to each other and additional

connections to ground

Ground return for the Receive RF input

Signal ground for the Receive mixers

DC and Signal ground for the Transmit RF Output buffer

DC power supply input to the interface logic and control registers. This

supply is not internally connected to any other supply pin, but its

voltage must be less than or equal to the VCC5 supply, and greater

than 2.7V. There must be a capacitor to ground from this pin to

decouple (bypass) noise and to stabilize the regulator

Ground for digital I/O circuits and control logic

Receive RF Input. Nominal impedance at 902 to 928MHz is 50W, with

a simple matching network required for optimum noise figure. This

input is to the base of an NPN transistor and should be AC coupled

Transmit RF Output. A broadband 50W output which sources 0dBm

over the 902 to 928MHz range. This output is an emitter follower and

should be AC coupled

Transmit Data input. Drives the transmit pulse shaping circuits. Serial

digital data on this pin becomes FSK modulation on the Transmit RF

output. Data timing is controlled by the logic timing on this pin. The

modulation deviation is determined by internal circuits. This is a

standard CMOS input referenced to VDD &VSS

Serial digital output after demodulation, chip rate filtering and center

data slicing. A CMOS level output (VSS to VDD) with controlled slew

rates. A low drive output designed to drive a PCB trace and a CMOS

logic input while generating minimal RFI. In digital test modes this pin

becomes a test access port controlled by the serial control bus

Enables the bandgap reference and voltage regulators when high.

Consumes only leakage current in standby mode when low. This is a

CMOS input, and the thresholds are referenced to VDD & VSS

Switches the transceiver between Transmit and Receive modes.

Circuits are powered up and signal paths reconfigured according to the

operating mode. This is a CMOS input, and the thresholds are

referenced to VDD & VSS

6

PRELIMINARY DATASHEET January, 2000

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