IS61LV12824-8B Просмотр технического описания (PDF) - Integrated Circuit Solution Inc

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IS61LV12824-8B

128K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY

Integrated Circuit Solution Inc 

IS61LV12824

WRITE CYCLE NO. 2(1) (CE Controlled: OE = HIGH or LOW: CE1, CE2 or CE2 Terminates Write)

ADDRESS

OE

t WC

VALID ADDRESS

t HA

CE1, CE2

CE2

LOW

HIGH

WE

DOUT

t SA

DATA UNDEFINED

t AW

t PWE1

t HZWE

DIN

HIGH-Z

t LZWE

t SD

t HD

DATAIN VALID

WRITE CYCLE NO. 2(1) (WE Controlled: OE = LOW, CE1, CE2 = LOW; CE2 = HIGH: WE TEMINATES WRITE)

t WC

ADDRESS

VALID ADDRESS

t HA

OE LOW

CE1, CE2 LOW

HIGH

CE2

WE

DOUT

t SA

DATA UNDEFINED

t AW

t PWE2

t HZWE

HIGH-Z

t LZWE

t SD

t HD

DIN

DATAIN VALID

Note:

1. The internal Write time is defined by the overlap of CE1 and CE2 = LOW, CE2 = HIGH and WE = LOW. All signals must be

in valid states to initiate a Write, but any can be deasserted to terminate the Write. The Data Input Setup and Hold timing is

referenced to the rising or falling edge of the signal that terminates the Write.

8

Integrated Circuit Solution Inc.

SR021-0B

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