LC4064ZE Просмотр технического описания (PDF) - Lattice Semiconductor

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LC4064ZE

1.8V In-System Programmable Ultra Low Power PLDs

Lattice Semiconductor 

Lattice Semiconductor

ispMACH 4000ZE Family Data Sheet

The number of BIE inputs, thus the number of Power Guard “Blocks” that can exist in a device, depends on the

device size. Table 8 shows the number of BIE signals available in the ispMACH 4000ZE family. The number of I/Os

available in each block is shown in the Ordering Information section of this data sheet.

Table 8. Number of BIE Signals Available in ispMACH 4000ZE Devices

Device

ispMACH 4032ZE

ispMACH 4064ZE

ispMACH 4128ZE

ispMACH 4256ZE

Number of Logic Blocks, Power

Guard Blocks and BIE Signals

Two (Blocks: A and B)

Four (Blocks: A, B, C and D)

Eight (Blocks: A, B, C, …, H)

Sixteen (Blocks: A, B, C, …, P)

Power Guard for Dedicated Inputs

Power Guard can optionally be applied to the dedicated inputs. The dedicated inputs and clocks are controlled by

the BIE of the logic blocks shown in Tables 9 and 10.

Table 9. Dedicated Clock Inputs to BIE Association

CLK/I

CLK0 / I

CLK1 / I

CLK2 / I

CLK3 / I

32 MC Block

A

A

B

B

64MC Block

A

B

C

D

128MC Block

A

D

E

H

256MC Block

A

H

I

P

Table 10. Dedicated Inputs to BIE Association

Dedicated Input

0

1

2

3

4

5

6

7

8

9

4064ZE Block

A

B

B

C

D

D

—

—

—

—

4128ZE Block

B

C

D

F

G

H

—

—

—

—

4256ZE Block

D

E

G

G

J

L

M

O

O

B

For more information on the Power Guard function refer to TN1174, Advanced Features of the ispMACH 4000ZE.

Global OE (GOE) and Block Input Enable (BIE) Generation

Most ispMACH 4000ZE family devices have a 4-bit wide Global OE (GOE) Bus (Figure 11), except the ispMACH

4032 device that has a 2-bit wide Global OE Bus (Figure 12). This bus is derived from a 4-bit internal global OE

(GOE) PT bus and two dual purpose I/O or GOE pins. Each signal that drives the bus can optionally be inverted.

Each GLB has a block-level OE PT that connects to all bits of the Global OE PT bus with four fuses. Hence, for a

256-macrocell device (with 16 blocks), each line of the bus is driven from 16 OE product terms. Figures 9 and 10

show a graphical representation of the global OE generation.

The block-level OE PT of each GLB is also tied to Block Input Enable (BIE) of that block. Hence, for a 256-macro-

cell device (with 16 blocks), each block's BIE signal is driven by block-level OE PT from each block.

12

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