MAX1203ACAP Просмотр технического описания (PDF) - Maxim Integrated

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MAX1203ACAP

5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface

Maxim Integrated 

MAX1202/MAX1203

5V, 8-Channel, Serial, 12-Bit ADCs

with 3V Digital Interface

CS

SCLK

DIN

DOUT

SSTRB

1

8

1

8

1

S CONTROL BYTE 0

S

CONTROL BYTE 1

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

CONVERSION RESULT 0

S CONTROL BYTE 2

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

CONVERSION RESULT 1

Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing

CS

SCLK

DIN

S CONTROL BYTE 0

S CONTROL BYTE 1

DOUT

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

CONVERSION RESULT 0

Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing

•••

•••

•••

B11 B10 B9 B8 B7 B6 B5 • • •

CONVERSION RESULT 1

down modes. For example, if the DIN word contains PD1

= 1, the chip remains powered up. If PD1 = 0, power-down

resumes after one conversion.

Hardware Power-Down

The SHDN pin places the converter into full power-down

mode. Unlike the software power-down modes, conversion

is not completed; it stops coincidentally with SHDN being

brought low. There is no power-up delay if an external ref-

erence, which is not shut down, is used. SHDN also selects

internal or external reference compensation (Table 7).

Power-Down Sequencing

The MAX1202/MAX1203’s automatic power-down modes

can save considerable power when operating at less than

maximum sample rates. The following sections discuss

the various power-down sequences.

Lowest Power at up to

500 Conversions per Channel per Second

Figure 14a depicts MAX1202 power consumption for one

or eight channel conversions using full power-down mode

and internal reference compensation. A 0.01μF bypass

capacitor at REFADJ forms an RC filter with the internal

20kΩ reference resistor, with a 0.2ms time constant. To

achieve full 12-bit accuracy, 10 time constants (or 2ms in

this example) are required for the reference buffer to set-

tle. When exiting FULLPD, waiting this 2ms in FASTPD

mode (instead of just exiting FULLPD mode and returning

to normal operating mode) reduces power consumption

by a factor of 10 or more (Figure 13).

Lowest Power at Higher Throughputs

Figure 14b shows power consumption with external ref-

erence compensation in fast power-down, with one and

eight channels converted. The external 4.7μF compen-

sation requires a 50μs wait after power-up. This circuit

combines fast multichannel conversion with the lowest

power consumption possible. Full power-down mode

can increase power savings in applications where the

MAX1202/MAX1203 are inactive for long periods of time,

but where intermittent bursts of high-speed conversion

are required.

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