74HC30D-Q100 Просмотр технического описания (PDF) - NXP Semiconductors.

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74HC30D-Q100

8-input NAND gate

NXP Semiconductors. 

Nexperia

74HC30-Q100; 74HCT30-Q100

8-input NAND gate

VI 90 %

negative

pulse

GND

VI

positive

pulse

10 %

GND

VM

10 %

tf

tr

90 %

VM

VI

G

RT

tW

tW

VCC

DUT

VM

tr

tf

VM

VO

CL

001aah768

Fig 6.

Test data is given in Table 9.

Definitions for test circuit:

RT = termination resistance should be equal to the output impedance Zo of the pulse generator.

CL = load capacitance including jig and probe capacitance.

Test circuit for measuring switching times

Table 9. Test data

Type

74HC30-Q100

74HCT30-Q100

Input

VI

VCC

3.0 V

tr, tf

6.0 ns

6.0 ns

Load

CL

15 pF, 50 pF

15 pF, 50 pF

Test

tPLH, tPHL

tPLH, tPHL

74HC_HCT30_Q100

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 30 January 2013

© Nexperia B.V. 2017. All rights reserved

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