V292PBC-40REVB2 Просмотр технического описания (PDF) - QuickLogic Corporation

Номер в каталоге

Компоненты Описание

Список матч

V292PBC-40REVB2

LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS

QuickLogic Corporation 

V292PBC Rev. B2

LOCAL BUS TO PCI BRIDGE

FOR DE-MULTIPLEXED A/D PROCESSORS

• Glueless interface between AMD’s Am29030/

40 processors and PCI bus

• Fully compliant with PCI 2.1 specification

• Configurable for primary master, bus master, or

target operation

• Up to 1Kbyte burst access support on both local

and PCI interface

• 576 bytes of programmable FIFO storage with

DYNAMIC BANDWIDTH ALLOCATION™

• Two channel DMA controller

• Enhanced support for 8/16-bit local bus devices

with programmable region size register

• 16 8-bit bi-directional mailbox registers with

doorbell interrupts

• Dual bi-directional address space remapping

• On-the-fly byte order (endian) conversion

• Optional power on serial EEPROM initialization

• I2O ATU and messaging unit including

hardware controlled circular queues

• Flexible PCI and local interrupt management

• Support for real-mode DOS "holes"

• Ability to generate both Type 0 and Type 1

configuration cycles

• 33MHz and 40MHz local bus versions available

with independent PCI operation up to 33MHz

• Low cost 160-pin EIAJ PQFP package

V292PBC provides the highest performance,

most flexible, and most economical method to

directly connect Am29030/40 processors to the

PCI bus. V292PBC is also a suitable candidate

for a variety of 32-bit de-multiplexed local bus

applications based on Motorola, IBM, DEC and

Hitachi embedded processors - where a minimal

amount of glue logic is required. V292PBC may

also be used in systems without a CPU for a

generic PCI master/target interface.

V292PBC Rev B2 is the first I2O ready PCI

bridge, fully backward compatible with V292PBC

Rev B1. The PCI bus can be run at the full

33MHz frequency, independent of local bus

clock rate. The overall throughput of the system

is dramatically improved by increasing the FIFO

depth and utilizing the unique DYNAMIC

BANDWIDTH ALLOCATION™ architecture.

Access to the PCI bus can be performed

through two programmable address apertures.

Two more apertures are provided for PCI-to-local

bus accesses. There are 32-bytes of read FIFO’s

in each direction, 16-byte dedicated for each

aperture. V292PBC also includes bi-directional

remapping capabilities, and on-the-fly byte order

conversion .

Two DMA channels are provided for autonomous

PCI-to-Local/Local-to-PCI transfers. Mailbox

registers and flexible PCI interrupt controllers are

also included to provide a simple mechanism to

emulate PCI device control ports.

The part is available in 160-pin low cost EIAJ

Plastic Quad Flat Pack (PQFP) package.

Am29030/40

CPU

V292BMC

D

MEMORY

R

CONTROL

A

M

ROM

TYPICAL APPLICATION

V292PBC

LOCAL TO

PCI BRIDGE

PCI

PERIPHERAL

PCI SLOT or EDGE CONNECTOR

Copyright © 1998, V3 Semiconductor Inc.

V292PBC Data Sheet Rev 2.4

1

V3 Semiconductor reserves the right to change the specifications of this product without notice.

V292PBC and V292BMC are trademarks of V3 Semiconductor. All other trademarks are the property of their respective owners.

Share Link: