V360EPC Просмотр технического описания (PDF) - QuickLogic Corporation
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V360EPC Datasheet PDF : 18 Pages
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V360EPC
Table 3: Signal Descriptions
Signal
AD[31:0]
C/BE[3:0]
PAR
FRAME
IRDY
TRDY
STOP
DEVSEL
IDSEL
REQ
GNT
PCLK
PRST
PERR
SERR
INT[A:D]
Type
PCI Bus Interface
Ra Description
PCI I/O Z Address and data, multiplexed on the same pins.
PCI I/O Z Bus Command and Byte Enables, multiplexed on the same pins.
PCI I/O Z Parity represents even parity across AD[31:0] and C/BE[3:0].
PCI I/O
Z
Cycle Frame indicates the beginning and burst length of an
access.
PCI I/O
Z
Initiator Ready indicates the initiating agent’s (bus master’s) ability
to complete the current data phase of the transaction.
PCI I/O
Z
Target Ready indicates the target agent’s (selected device’s) abil-
ity to complete the current data phase of the transaction.
PCI I/O
Z
Stop indicates the current target is requesting the master to stop
the current transaction (retry or disconnect).
PCI I/O
Device Select, when actively driven by a target, indicates the driv-
Z
ing device has decoded its address as the target of the current
access. As an input to the initiator, DEVSEL indicates whether
any device on the bus has been selected.
PCI I
Initialization Device Select is used as a chip select during configu-
ration read and write transactions. It must be driven high in order
to access the chip’s internal configuration space.
PCI O
Z
Request indicates to the arbiter that this agent requests use of the
bus.
PCI I
Grant indicates to the agent that access to the bus has been
granted.
PCI I
PCLK provides timing for all transactions on the PCI bus.
PCI I/O
Acts as an input when RDIR is high, an output when RDIR is low.
Z/L As an input it is asserted low to bring all internal EPC operation to
a reset state.
PCI I/O
Z
Parity Error is used to report data parity errors during all PCI
transactions except a Special Cycle.
PCI I/OD
System Error is used to report address parity errors, data parity
Z errors on the Special Cycle command, or any other system error
where the result will be catastrophic.
PCI I/OD Z Level-sensitive interrupt requests may be received or generated.
Copyright © 1998, V3 Semiconductor Corp.
V360EPC Data Sheet Rev 1.2
3
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