LH532000B-1 Просмотр технического описания (PDF) - Sharp Electronics

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LH532000B-1

CMOS 2M (256K × 8/128K × 16) MROM

Sharp Electronics 

CMOS 2M MROM

LH532000B-1

A16 32

A15 33

A14 34

A13 35

A12 36

A11 37

A10 38

A9 39

A8 40

A7 2

A6 3

A5 4

A4 5

A3 6

A2 7

A1 8

A0 9

MEMORY

MATRIX

(262,144 x 8 )

(131,072 x 16 )

COLUMN SELECTOR

SENSE AMPLIFIER

CE 10

OE/OE 12

OE1/OE1/DC 1

BYTE 31

CE

BUFFER

TIMING

GENERATOR

OE

BUFFER

BYTE/WORD

SWITCHOVER

CIRCUIT

ADDRESS

BUFFER

DATA SELECTOR/OUTPUT BUFFER

21

11

30

29

VCC GND GND

A-1

13 15 17 19 22 24 26 28 14 16 18 20 23 25 27 29

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

NOTE: Pin numbers apply to 40-pin DIP or SOP.

532000B1-3

Figure 3. LH532000B-1 Block Diagram

PIN DESCRIPTION

SIGNAL

A–1 – A16

D0 – D15

BYTE

CE

PIN NAME

Address input

Data output

Byte/word mode switch

Chip enable input

NOTE

1

1

1

SIGNAL

OE/OE

OE1/OE1/DC

VCC

GND

PIN NAME

Output enable input

Output enable input

Power supply (+5 V)

Ground

NOTES:

1. D15/A–1 pin becomes LSB address input (A–1) when the BYTE pin is set to be LOW in byte mode,

and data output (D15) when set to be HIGH in word mode.

2. The active levels of OE/OE and OE1/OE1/DC are mask-programmable.

NOTE

2

2

3

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