LH532000BD Просмотр технического описания (PDF) - Sharp Electronics

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LH532000BD

CMOS 2M (256K × 8/128K × 16) MROM

Sharp Electronics 

CMOS 2M MROM

LH532000B

A16 32

A15 33

A14 34

A13 35

A12 36

A11 37

A10 38

A9 39

A8 40

A7 2

A6 3

A5 4

A4 5

A3 6

A2 7

A1 8

A0 9

MEMORY

MATRIX

(262,144 x 8)

(131,072 x 16)

COLUMN SELECTOR

29 D15

27 D14

25 D13

23 D12

20 D11

18 D10

16 D9

14 D8

28 D7

26 D6

24 D5

22 D4

19 D3

17 D2

15 D1

13 D0

CE 10

CE

BUFFER

TIMING

GENERATOR

SENSE AMPLIFIER

OE1/OE1/DC 1

OE/OE 12

OE

BUFFER

BYTE 31

BYTE/WORD

SWITCHOVER

CIRCUIT

ADDRESS

BUFFER

29

A-1

NOTE: Pin numbers apply to the 40-pin DIP or SOP.

21 11 30

VCC GND

Figure 3. LH532000B Block Diagram

PIN DESCRIPTION

SIGNAL

PIN NAME

NOTE

SIGNAL

PIN NAME

A–1

Address input (BYTE mode)

1

A0 – A16

Address input

D0 – D15 Data output

1

CE

Chip enable input

OE/OE

Output enable input

2

OE1/OE1/DC

BYTE

VCC

GND

Output enable input or

Don’t care

Byte/word mode switch

Power supply (+5 V)

Ground

NOTES:

1. D15/A–1 pin becomes LSB address input (A–1) when the bit configuration is set in byte mode,

and data output (D15) when in word mode. BYTE input pin selects bit configuration.

2. The active levels of OE/OE and OE1/OE1/DC are mask-programmable.

Selecting DC allows the outputs to be active for both high and low levels applied to this pin.

It is recommended to apply either a HIGH or a LOW to the DC pin.

532000B-2

NOTE

2

3

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