CS5505-AP Просмотр технического описания (PDF) - Cirrus Logic
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CS5505-AP Datasheet PDF : 40 Pages
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CS5505/6/7/8
CS5505/6/7/8
5V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ± 10%;
VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2)
Parameter
Symbol Min
Typ
Max Units
SSC Mode (M/SLP = VD+)
Access Time:
CS Low to SDATA out (DRDY = low) tcsd1
-
DRDY falling to MSB (CS = low) tdfd
-
-
2/fclk
ns
2/fclk
3/fclk
ns
SDATA Delay Time:
SCLK falling to next SDATA bit tdd1
-
80
250
ns
SCLK Delay Time
SDATA MSB bit to SCLK rising tcd1
-
1/fclk
-
ns
Serial Clock (Out)
Pulse Width High tph1
-
1/fclk
-
ns
Pulse Width Low tpl1
-
1/fclk
-
ns
Output Float Delay:
CS high to output Hi-Z (Note 16) tfd1
-
-
2/fclk
ns
SCLK rising to SDATA Hi-Z tfd2
-
1/fclk
-
ns
SEC Mode (M/SLP = DGND)
Serial Clock (In)
fsclk
0
-
2.5 MHz
Serial Clock (In)
Pulse Width High tph2
200
-
Pulse Width Low tpl2
200
-
-
ns
-
ns
Access Time:
CS Low to data valid (Note 17) tcsd2
-
60
200
ns
Maximum Delay time:
(Note 18)
SCLK falling to new SDATA bit tdd2
-
150
310
ns
Output Float Delay:
CS high to output Hi-Z (Note 16) tfd3
-
60
150
ns
SCLK falling to SDATA Hi-Z tfd4
-
160
300
ns
Notes: 16. If CS is returned high before all data bits are output, the SDATA and SCLK outputs will complete the
current data bit and then go to high impedance.
17. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high
for 2 clock cycles. The propagation delay time may be as great as 2 fclk cycles plus 200 ns. To
guarantee proper clocking of SDATA when using asynchronous CS, SCLK(i) should not be taken high
sooner than 2 fclk + 200 ns after CS goes low.
18. SDATA transitions on the falling edge of SCLK. Note that a rising SCLK must occur to enable the
serial port shifting mechanism before falling edges can be recognized.
DS59F45
9
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