ADV7480WBBCZ-RL Просмотр технического описания (PDF) - Analog Devices
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ADV7480WBBCZ-RL Datasheet PDF : 19 Pages
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Data Sheet
ADV7480
Parameter
Symbol Test Conditions/Comments
Min
Typ
Max
Unit
8-BIT DIGITAL INPUT PORT2
DVDDIO = 3.14 V to 3.46 V
LLC High Time3
t21
45
55
% duty
cycle
LLC Low Time3
45
55
% duty
cycle
SDR and DDR Modes Setup Time
t22
Data latched on rising edge
1
ns
SDR and DDR Modes Hold Time
t23
Data latched on rising edge
1
ns
DDR Mode Setup Time
t24
Data latched on falling edge
1
ns
DDR Mode Hold Time
t25
Data latched on falling edge
1
ns
8-BIT DIGITAL OUTPUT PORT2
DVDDIO = 3.14 V to 3.46 V
LLC High Time
t26
40
60
% duty
cycle
LLC Low Time
40
60
% duty
cycle
SDR Modes Setup Time4, 5
t36
At P0 to P7 output pin, data latched 1.98
ns
on rising edge
SDR Modes Hold Time4, 5
t37
At P0 to P7 output pin, data latched 2.50
ns
on rising edge
DDR Modes Setup Time4, 5
t27
At P0 to P7 output pin, data latched 1.66
ns
on rising edge
DDR Modes Hold Time4, 5
t28
At P0 to P7 output pin, data latched 3.52
ns
on rising edge
DDR Mode Setup Time4, 5
t29
At P0 to P7 output pin, data latched 1.71
ns
on falling edge
DDR Modes Hold Time4, 5
t30
At P0 to P7 output pin, data latched 3.17
ns
on falling edge
I2S PORT, MASTER MODE
I2S_SCLK High Time
t31
45
55
% duty
cycle
I2S_SCLK Low Time
45
55
% duty
cycle
I2S_LRCLK Data Transition Time
t32
End of valid data to I2S_SCLK falling
edge
10
ns
t33
I2S_SCLK falling edge to start of valid
data
10
ns
I2S_SDATA Data Transition Time
t34
End of valid data to I2S_SCLK falling
edge
5
ns
t35
I2S_SCLK falling edge to start of valid
data
5
ns
1 Required by design.
2 The 8-bit digital input/output port is only available when the DVDDIO supply is between 3.14 V and 3.46 V.
3 Guaranteed by design.
4 These specifications only apply when the LLC_DLL_PHASE[4:0] (IO Map, Register 0x0C[4:0]) is set to 00000
5 Guaranteed by lab characterization.
Rev. 0 | Page 9 of 19
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