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ADAS3022BCPZ

16-Bit, 1 MSPS, 8-Channel, Data Acquisition System

Analog Devices 

ADAS3022

500µA IOL

TO SDO

CL

50pF

1.4V

500µA IOH

Figure 2. Load Circuit for Digital Interface Timing

Data Sheet

30% VIO

tDELAY

2V OR VIO – 0.5V1

0.8V OR 0.5V2

70% VIO

tDELAY

2V OR VIO – 0.5V1

0.8V OR 0.5V2

12V IF VIO > 2.5V; VIO – 0.5V IF VIO < 2.5V.

20.8V IF VIO > 2.5V; 0.5V IF VIO < 2.5V.

Figure 3. Voltage Levels for Timing

SOC

POWER

UP

PHASE

CNV

BUSY

CS

SCK

DIN

SDO

CONVERSION (n – 1)

UNDEFINED

tACQ

EOC

SOC

ACQUISITION (n)

UNDEFINED

tDDC

NOTE 1

CONVERSION (n)

UNDEFINED

tCYC

EOC

tQUIET

NOTE 2

tDAC

NOTE 1

ACQUISITION (n + 1)

UNDEFINED

NOTE 4

X

CFG

INVALID

DATA

INVALID

1

CFG (n + 2)

DATA (n – 1)

INVALID

NOTE 5

tAD

tDDCA

NOTE 2

CFG (n + 2)

DATA (n – 1)

INVALID

16/32

NOTE 3

1

CFG (n + 3)

DATA (n)

INVALID

CONVERSION (n + 1)

UNDEFINED

16

CFG (n + 3)

DATA (n)

INVALID

EOC

PHASE

CNV

BUSY

ACQUISITION

(n + 2)

CONVERSION

(n + 2)

EOC

ACQUISITION

(n + 3)

CONVERSION

(n + 3)

EOC

ACQUISITION

(n + 4)

CONVERSION

(n + 4)

CS

1

SCK

16

1

16

1

DIN

CFG (n + 4)

CFG (n + 4)

CFG (n + 5)

CFG (n + 5)

SDO

DATA (n + 1)

INVALID

DATA (n + 1)

INVALID

DATA (n + 2)

DATA (n + 2)

NOTES

1. DATA ACCESS CAN OCCUR DURING A CONVERSION ( tDDC), AFTER A CONVERSION (tDAC), OR BOTH DURING AND AFTER A CONVERSION.

THE CONVERSION RESULT AND THE CFG REGISTER ARE UPDATED AT THE END OF A CONVERSION (EOC).

2.

DATA ACCESS CAN

TIME CAN BE USED

ALSO OCCUR UP TO

TO ACQUIRE DATA.

tDDCA

WHILE

BUSY

IS

ACTIVE

(SEE

THE

DIGITAL

INTERFACE

SECTION

FOR

DETAILS).

ALL

OF

THE

BUSY

3. A TOTAL OF 16 SCK FALLING EDGES IS REQUIRED FOR A CONVERSION RESULT. AN ADDITIONAL 16 EDGES ARE REQUIRED TO

READ BACK THE CFG RESULT ASSOCIATED WITH THE CURRENT CONVERSION.

4. CS CAN BE HELD LOW OR CONNECTED TO CNV. CS WITH FULL INDEPENDENT CONTROL IS SHOWN IN THIS FIGURE.

5. FOR OPTIMAL PERFORMANCE, DATA ACCESS SHOULD NOT OCCUR DURING THE SAMPLING EDGE. A MINIMUM TIME

OF THE APERTURE DELAY (tAD) SHOULD ELAPSE PRIOR TO DATA ACCESS.

Figure 4. General Timing Diagram

CFG (n + 6)

DATA (n + 3)

CFG (n + 6)

DATA (n + 3)

Rev. D | Page 8 of 42

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