74ABT16823ADGG,118 Просмотр технического описания (PDF) - NXP Semiconductors.

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74ABT16823ADGG,118

18-bit bus interface D-type flip-flop with reset and enable (3-State)

NXP Semiconductors. 

Philips Semiconductors

18-bit bus-interface D-type flip-flop

with reset and enable (3-State)

Product data

74ABT16823A

AC WAVEFORMS

For all waveforms, VM = 1.5 V.

The shaded areas indicate when the input is permitted to change for predictable output performance.

nCP

nQn

1/fMAX

VM

tw

tPHL

VM

VM

tPLH

VM

3.0V or VCC

whichever

is less

0V

VOH

0V

SH00017

Waveform 1. Propagation Delay, Clock Input to Output,

Clock Pulse Width, and Maximum Clock Frequency

nMR

nCP

nQn

VM

tw

tPHL

VM

tREC

VM

VM

3.0V or VCC

whichever

is less

0V

3.0V or VCC

whichever

is less

0V

VOH

0V

SH00018

Waveform 2. Master Reset Pulse WIdth, Master Reset to

Output Delay and Master Reset to Clock Recovery Time

nOE

VM

tPZH

VM

tPHZ

3.0V or VCC

whichever

is less

0V

VOH

VM

VOH–0.3V

nQx

0V

SH00020

Waveform 4. 3-State Output Enable Time to HIGH Level

and Output Disable Time from HIGH Level

nOE

nQx

VM

tPZL

VM

VM

tPLZ

3.0V or VCC

whichever

is less

0V

3.0V or VCC

whichever

is less

VOL +0.3V

VOL

SH00021

Waveform 5. 3-State Output Enable Time to LOW Level

and Output Disable Time from LOW Level

nDx,

nCE

nCP

VM VM

VM VM

ts(H)

th(H)

VM

ts(L)

th(L)

VM

3.0V or VCC

whichever

is less

0V

3.0V or VCC

whichever

is less

0V

SH00019

Waveform 3. Data Set-up and Hold Times

2004 Feb 02

8

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