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UT8Q1024K8-UPA

SRAM, high-performance 1M byte (8Mbit) CMOS static RAM

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A(18:0)

tAVAV

DQ(7:0)

Previous Valid Data

Assumptions:

1 . En andG < VIL (max) and Wn > VIH (min)

tA X Q X

Valid Data

tAVQV

Figure 4a. SRAM Read Cycle 1: Address Access

A(18:0)

En

DQ(7:0)

t E T QX

tE T QV

tEFQZ

DATA VALID

Assumptions:

1. G < V IL (max) and Wn > VIH (min)

Figure 4b. SRAM Read Cycle 2: Chip Enable-Controlled Access

A(18:0)

tAVQV

G

DQ(7:0)

Assumptions:

1 . En < VIL (max) andWn > VIH (min)

tGLQX

tGLQV

tGHQZ

DATA VALID

Figure 4c. SRAM Read Cycle 3: Output Enable-Controlled Access

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