MB90091A Просмотр технического описания (PDF) - Fujitsu

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MB90091A

Intelligent on-screen display controller (IOSDC)

Fujitsu 

MB90091A

s PIN DESCRIPTION

Pin No.

DIP

QFP

8

1

9

2

10

3

11

4

13

6

15

8

16

9

18

11

19

12

20

13

21

14

22

15

23

16

24

17

25

18

26

19

28

21

29

22

30

23

31

24

32

25

Pin name I/O

Function

HSYNC

VSYNC

EVEN

FLTIN

FLTOUT

FH

RESET

RD0

RD1

RD2

RD3

RD4

RD5

RD6

RD7

TEST

TA16

TA17

TA18

FCS

TCS

I

Horizontal sync signal input pin

Dot clock generation is based on the cycle of the signal.

I Vertical sync signal input pin

Field control signal input pin

Input of an “L” level signal to this pin causes the font ROM address

LSB pin (RA0) to output an “L” level signal.

I Input of an “H“ level signal to this pin causes the font ROM address

LSB pin (RA0) to output an “H” level signal (when normal-size

characters are displayed).

This pin is disabled in noninterlaced mode.

O

Output pin for horizontal-sync phase comparison result signal

This pin is connected to an external lowpass filter.

I

Internal VCO voltage input pin

This pin inputs the voltage signal from the external lowpass filter.

O Output pin for AFC-generated horizontal sync signal

I

Reset pin

This pin is enabled after release from a power-on reset.

External ROM data input pin

I This pin inputs data from external font ROM or external command

data ROM.

I

Test signal input pin

This pin inputs an “L” level (fixed) signal during normal operation.

O Test signal output pin

O External font ROM chip select pin

O Chip select pin for external command table ROM

(Continued)

5

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