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LH543620P-20

1024 × 36 Synchronous FIFO

Sharp Electronics 

1024 × 36 Synchronous FIFO

LH543620

Writing to the Mailbox is enabled from the Input Port

when the Input Port address field ADI[2:0] = 6. The write

operation is synchronous to the rising edge of CKI.

When writing to the Mailbox, the status flags are

changed as follows:

MEF is deasserted HIGH on the rising edge of CKO.

MFF is asserted LOW on the rising edge of CKI.

A Mailbox read is enabled from the Output Port, when

the Output Port address field ADO[2:0] = 6. The Read

operation is synchronized to CKO.

When reading the Mailbox, the status flags are

changed as follows:

MEF is asserted LOW on the rising edge of CKO.

MFF is deasserted HIGH on the rising edge of CKI.

After reset the Mailbox is empty (i.e., MFF = HIGH,

MEF = LOW).

When using Mailbox, the transmitter side can transfer

a message to the receiver side without interrupting the

data in the FIFO memory array.

DATA BYPASS MODE

Data Bypass mode is selected when BYE = LOW. In

this mode, data may be transferred asynchronously from

the Input Port to the Output Port. The device may be

placed in Data Bypass mode without voiding the contents

of the FIFO memory array, the Mailbox Register, or the

Resource Register. However, if the input is enabled

(ENI1,2 = HIGH) then the input data D is also written to

the FIFO memory array on the rising edge of CKI. If the

Output is enabled, (ENO1,2 = HIGH) then the input data

D is transferred to the output buffer, and the Read Pointer

is incremented by CKO. The control signal OE is function-

ing when BYE is asserted.

The recommended control setting for bypass is:

ENI = LOW, ENO = LOW, ADI[2:0] = 7,

ADO[2:0] = 7, OE = LOW, BYE = LOW

OPERATIONAL MODES AND CONFIGURATIONS

Interlocked Width Expansion (Figure 8A)

Two LH543620s may be configured to expand the

width to 72 bits. This is accomplished by:

Cross-connecting the FF output of each FIFO to ENI1

(or ENI2) input of the other FIFO.

Cross-connecting the EF output of each FIFO to ENO1

(or ENO2) input of the other FIFO.

The composite status flags are the OR function of the

individual flags.

Pipeline Cascading Mode and ‘Two-Dimension’

Pipeline Cascading Mode (Figure 8B and 8C)

Depth cascading is accomplished by:

Setting the upper FIFO into cascade mode:

RTMD[1:0] = 0

Connecting the same free-running clock to CKO of the

upper FIFO and to CKI input of the lower FIFO.

Connecting the AE output of the upper FIFO to ENI1

input (or ENI2) of the lower FIFO.

Connecting the FF output of the lower FIFO to ENO1

input (or ENO2) of the upper FIFO.

NOTE: RTMD[1:0] should remain stable during cascade

mode operation (i.e., remain low).

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