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LH543620

1024 × 36 Synchronous FIFO

Sharp Electronics 

1024 × 36 Synchronous FIFO

LH543620

PIN NAME

AE

EF

PF

MEF

VCC

VSS

DESCRIPTION

STATUS FLAGS SYNCHRONOUS TO THE OUTPUT CLOCK

Almost-Empty Flag. The AE flag has two modes of operation depending on the RTMD[1:0]

setting.

1. RTMD[1:0] ≠ 0: AE is a standard Almost-Empty Flag. When asserted LOW, AE implies that

there are at most ‘q’ 36-bit words in the FIFO memory array, where ‘q’ is Almost-Empty-Offset-

Value register value. In this mode AE has two synchronization options depending on the setting of

Bit 2 of the control register.

Bit 2 = 0 (Default) Asynchronous Mode

Bit 2 = 1 Synchronous Mode: AE is synchronous to the rising edge of CKO.

2. RTMD[1:0] = 0: AE is a handshake signal for cascading.

Empty Flag. EF is synchronous to the rising edge of CKO. When asserted LOW, all 1024

36-bit words are vacant. When asserted, EF disables the FIFO Read operation.

Parity-Error Flag. PF is synchronized to the rising edge of CKO. When asserted LOW, PF

implies that a parity error has occurred in at least one 9-bit byte within a 36-bit word read from the

FIFO memory array. If there are no errors, it is deasserted HIGH. When an error is detected, the

parity check result of each 9-bit byte of the 36-bit output word is written to the parity register. The

content of the parity register is frozen until read. The PF signal is delayed by one CKO cycle

compared to the output data (i.e., if the PF is asserted, there was an error in the previous word).

Mailbox-Empty Flag. MEF is synchronous to the rising edge of CKO. When asserted LOW, MEF

indicates that there is no new mail word in the mailbox.

VOLTAGES AND GROUNDS

Positive Power.

Ground.

OPERATIONAL DESCRIPTION

The LH543620 has four operating modes: Normal

Mode, Programmable Resource Registers, Mailbox, and

Data Bypass.

NORMAL MODE

Normal FIFO operation refers to Read and Write op-

erations to the FIFO memory array. Data Write operations

into the FIFO memory array occur at the rising edge of

CKI. The operation is enabled if both ENI1 and ENI2 are

asserted HIGH. Data Read operations from the FIFO

memory occur at the rising edge of CKO. The operation

is enabled if both ENO1 and ENO2 are asserted HIGH.

The FIFO write and read operations are supported by

the following mechanisms: Byte-Order-Reversal and Bus

Funneling/Defunneling Functions, Status Flags, Retrans-

mit Mechanism, Parity Checking, and Parity Generation.

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