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7493

4-bit binary ripple counter

NXP Semiconductors. 

Philips Semiconductors

4-bit binary ripple counter

Product specification

74HC/HCT93

FEATURES

• Various counting modes

• Asynchronous master reset

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT93 are high-speed

Si-gate CMOS devices and are pin

compatible with low power Schottky

TTL (LSTTL). They are specified in

compliance with JEDEC standard

no. 7A.

The 74HC/HCT93 are 4-bit binary

ripple counters. The devices consist

of four master-slave flip-flops

internally connected to provide a

divide-by-two section and a

divide-by-eight section. Each section

has a separate clock input (CP0 and

CP1) to initiate state changes of the

counter on the HIGH-to-LOW clock

transition. State changes of the Qn

outputs do not occur simultaneously

because of internal ripple delays.

Therefore, decoded output signals

are subject to decoding spikes and

should not be used for clocks or

strobes.

A gated AND asynchronous master

reset (MR1 and MR2) is provided

which overrides both clocks and

resets (clears) all flip-flops.

Since the output from the

divide-by-two section is not internally

connected to the succeeding stages,

the device may be operated in various

counting modes. In a 4-bit ripple

counter the output Q0 must be

connected externally to input CP1.

The input count pulses are applied to

clock input CP0. Simultaneous

frequency divisions of 2, 4, 8 and 16

are performed at the Q0, Q1, Q2 and

Q3 outputs as shown in the function

table. As a 3-bit ripple counter the

input count pulses are applied to input

CP1.

Simultaneous frequency divisions of

2, 4 and 8 are available at the Q1, Q2

and Q3 outputs. Independent use of

the first flip-flop is available if the reset

function coincides with reset of the

3-bit ripple-through counter.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

SYMBOL PARAMETER

CONDITIONS

tPHL/ tPLH

fmax

CI

CPD

propagation delay CP0 to Q0

maximum clock frequency

input capacitance

power dissipation capacitance per package

CL = 15 pF; VCC = 5 V

notes 1 and 2

TYPICAL

HC

12

100

3.5

22

HCT

15

77

3.5

22

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz; fo = output frequency in MHz

∑ (CL × VCC2 × fo) = sum of outputs

CL = output load capacitance in pF; VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC − 1.5 V

UNIT

ns

MHz

pF

pF

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

December 1990

2

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