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MWCT1001AVLH

Automotive Wireless Transmitter Controller

Freescale Semiconductor 

53. 1 LSB = (VREFH - VREFL)/2N.

54. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11).

55. Input data is 100 Hz sine wave; ADC conversion clock < 12 MHz.

56. System clock = 4 MHz, ADC clock = 2 MHz, AVG = Max, Long Sampling = Max.

57. Settling time is swing range from VSSA to VDDA.

58. LSB = 0.806 mV.

59. No guaranteed specification within 5% of VDDA or VSSA.

60. Typical supply current with high-speed mode is 300 µA, typical supply current with low-speed mode is 36 µA on WCT1001A.

Maximum supply current with high-speed mode is 200 µA, maximum supply current with low-speed mode is 20 µA on WCT1003A.

61. Typical hysteresis is measured with input voltage range limited to 0.7 to VDD-0.7 V. On WCT1001A, typical 25 mV for CR0[HYSTCTR]

= 01, typical 55 mV for CR0[HYSTCTR] = 10, typical 80 mV for CR0[HYSTCTR] = 11. On WCT1003A, typical 10 mV for CR0[HYSTCTR] =

01, typical 20 mV for CR0[HYSTCTR] = 10, typical 30 mV for CR0[HYSTCTR] = 11.

62. Signal swing is 100 mV.

63. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN, VRSEL,

PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.

64. 1 LSB = Vreference/64.

65. Reference IPbus clock of 100 MHz in NanoEdge Placement mode.

66. Temperature and voltage variations do not affect NanoEdge Placement step size.

67. Powerdown to NanoEdge mode transition.

68. Ttimer = Timer input clock cycle. For 100 MHz operation, Ttimer = 10 ns.

69. For QSPI specifications, all data with xx/xx format, the former is for WCT1001A, the latter is for WCT1003A.

70. fMAX_SCI is the frequency of operation of the SCI clock in MHz, which can be selected as the bus clock or 2x bus clock for the device.

71. WCT1001A supports maximum 1.5 us pulse filtered, and WCT1003A supports maximum 2 us pulse filtered.

72. The master mode IIC deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this

address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL lines.

73. The maximum tHD_DAT must be met only if the device does not stretch the LOW period (tSCL_LOW) of the SCL signal.

74. Input signal Slew = 10 ns and Output Load = 50 pF

75. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.

76. A Fast mode IIC bus device can be used in a Standard mode IIC bus system, but the requirement tSU_DAT ≥ 250 ns must then be

met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the

LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU_DAT = 1000 + 250 = 1250 ns

(according to the Standard mode IIC bus specification) before the SCL line is released.

77. Cb = total capacitance of the one bus line in pF.

2.3 Thermal Operating Characteristics

Table 7. General Thermal Characteristics

Symbol

Description

Min

TJ

Die junction temperature

-40

TA

Ambient temperature

-40

Max

Unit

125

°C

105

°C

3 Typical Performance Characteristics

3.1 System Efficiency

The typical maximum system efficiency (receiver output power vs. transmitter input power) on Freescale

WCT100xA A13 transmitter reference solution is shown in Figure 1, using a test receiver (aka Rx, low

power receiver) under resistive load.

Automotive Wireless Transmitter Controller, Rev. 1.0, 08/2014

Freescale Semiconductor

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