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MAX548

8-Bit Parallel DAC in QSOP-16 Package

Maxim Integrated 

8-Bit Parallel DAC in

QSOP-16 Package

_______________Detailed Description

The MAX5480 is an 8-bit multiplying digital-to-analog

converter (DAC) that consists of a thin-film R-2R resistor

array with CMOS current steering switches. Figure 3

shows a simplified schematic of the DAC. The inverted

R-2R ladder divides the voltage or current reference in

a binary manner among the eight steering switches.

The magnitude of the current appearing at either OUT

terminal depends on the number of switches selected;

therefore, the output is an analog representation of the

digital input. The two OUT terminals must be held at the

same potential so a constant current is maintained in

each ladder leg. This makes the REF input current inde-

pendent of switch state and also ensures that the

MAX5480 maintains its excellent linearity performance.

Interface-Logic Information

Mode Selection

The inputs CS and WR control the MAX5480’s operat-

ing mode (see Table 1).

Write Mode

When CS and WR are both low, the MAX5480 is in write

mode, and its analog output responds to data activity at

the D0–D7 data-bus inputs. In this mode, the data

latches are transparent (see Tables 2 and 3).

Hold Mode

In hold mode, the MAX5480 retains the data that was

present on D0–D7 just prior to CS or WR assuming a

high state. The analog output remains at the value cor-

responding to the digital code locked in the data latch.

__________Applications Information

Using the MAX5480 in Voltage-

Output Mode (Single Supply)

The MAX5480 can be used either as a current-output

DAC (Figures 1 and 6) or as a voltage-output DAC

(Figures 2 and 5).

To use the MAX5480 in voltage mode, connect OUT1 to

the reference input and connect OUT2 to ground. REF,

now the DAC output, is a voltage source with a con-

stant output resistance of 10kΩ (nominally). This output

is often buffered with an op amp (Figure 5).

An advantage of voltage-mode operation is single-

supply operation for the complete circuit; i.e., a nega-

tive reference is not required for a positive output. It is

important to note that the range of the reference is

restricted in voltage mode. The reference input (voltage

at OUT1) must always be positive and is limited to no

more than VDD - 3V. If the reference voltage exceeds

this value, linearity is degraded.

VREF VDD

DATA

INPUTS

R1

2k

15

REF

4–11 D7–D0

R2

14

VDD

16

RFB

1k

1 10pF

OUT1

12 CS MAX5480

OUT2

2

MAX4330

VOUT

13 WR

GND

3

R1 AND R2 USED ONLY IF GAIN

ADJUSTMENT IS REQUIRED.

Figure 1. Unipolar Binary Operation (Two-Quadrant Multiplication)

REF

INPUT*

16

RFB

1

OUT1

2 OUT2

MAX5480

WR CS GND

13 12 3

*(VDD - 3V, max)

+5V

14

VDD

REF

15

OUTPUT

VOLTAGE

(10kΩ OUTPUT

RESISTANCE)

D7–D0

4–11

DATA IN

Figure 2. Typical Operating Circuit (Voltage Mode—Unbuffered)

Table 1. Mode-Selection Table

CS WR MODE

DAC Response

L

L

Write

DAC responds to data bus

(D0–D7) inputs.

H

X

Hold Data bus (D0–D7) is locked out;

X

H

Hold DAC holds last data present

when CS or WR assumed high

state.

L = Low State, H = High State, X = Don’t Care

4 _______________________________________________________________________________________

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