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XRT83VSH28

8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT

Exar Corporation 

PRELIMINARY

XRT83VSH28

REV. P1.0.0

8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT

GENERAL DESCRIPTION................................................................................................. 1

APPLICATIONS ............................................................................................................................................... 1

FIGURE 1. BLOCK DIAGRAM OF THE XRT83VSH28 E1 LIU (HOST MODE)........................................................................................ 1

FIGURE 2. BLOCK DIAGRAM OF THE XRT83VSH28 E1 LIU (HARDWARE MODE) ............................................................................... 2

FEATURES ..................................................................................................................................................... 3

ORDERING INFORMATION .................................................................................................................... 3

PIN DESCRIPTION BY FUNCTION................................................................................... 5

RECEIVE SECTION ......................................................................................................................................... 5

TRANSMIT SECTION ....................................................................................................................................... 8

PARALLEL MICROPROCESSOR INTERFACE..................................................................................................... 10

JITTER ATTENUATOR .................................................................................................................................... 12

CLOCK SYNTHESIZER................................................................................................................................... 12

ALARM FUNCTIONS/REDUNDANCY SUPPORT ................................................................................................. 14

SERIAL MICROPROCESSOR INTERFACE ......................................................................................................... 16

POWER AND GROUND .................................................................................................................................. 16

FUNCTIONAL DESCRIPTION ......................................................................................... 19

1.0 HARDWARE MODE VS HOST MODE ................................................................................................ 19

1.1 FEATURE DIFFERENCES IN HARDWARE MODE ...................................................................................... 19

TABLE 1: DIFFERENCES BETWEEN HARDWARE MODE AND HOST MODE .......................................................................................... 19

2.0 RECEIVE PATH LINE INTERFACE .................................................................................................... 20

FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE PATH...................................................................................................... 20

2.1 LINE TERMINATION (RTIP/RRING) .............................................................................................................. 20

2.1.1 CASE 1: INTERNAL TERMINATION.......................................................................................................................... 20

TABLE 2: SELECTING THE INTERNAL IMPEDANCE ............................................................................................................................. 20

FIGURE 4. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION .................................................................................... 20

2.1.2 CASE 2: INTERNAL TERMINATION WITH ONE EXTERNAL FIXED RESISTOR FOR ALL MODES .................... 21

TABLE 3: SELECTING THE VALUE OF THE EXTERNAL FIXED RESISTOR ............................................................................................. 21

FIGURE 5. TYPICAL CONNECTION DIAGRAM USING ONE EXTERNAL FIXED RESISTOR ....................................................................... 21

2.2 CLOCK AND DATA RECOVERY ................................................................................................................... 22

FIGURE 6. RECEIVE DATA UPDATED ON THE RISING EDGE OF RCLK .............................................................................................. 22

FIGURE 7. RECEIVE DATA UPDATED ON THE FALLING EDGE OF RCLK ............................................................................................ 22

TABLE 4: TIMING SPECIFICATIONS FOR RCLK/RPOS/RNEG .......................................................................................................... 22

2.2.1 RECEIVE SENSITIVITY .............................................................................................................................................. 23

FIGURE 8. TEST CONFIGURATION FOR MEASURING RECEIVE SENSITIVITY........................................................................................ 23

2.2.2 INTERFERENCE MARGIN ......................................................................................................................................... 23

FIGURE 9. TEST CONFIGURATION FOR MEASURING INTERFERENCE MARGIN .................................................................................... 23

2.2.3 GENERAL ALARM DETECTION AND INTERRUPT GENERATION ........................................................................ 23

2.3 RECEIVE JITTER ATTENUATOR .................................................................................................................. 24

2.4 HDB3 DECODER ............................................................................................................................................ 25

2.5 RPOS/RNEG/RCLK ........................................................................................................................................ 25

FIGURE 10. SINGLE RAIL MODE WITH A FIXED REPEATING "0011" PATTERN................................................................................... 25

FIGURE 11. DUAL RAIL MODE WITH A FIXED REPEATING "0011" PATTERN...................................................................................... 25

2.6 RXMUTE (RECEIVER LOS WITH DATA MUTING) ....................................................................................... 26

FIGURE 12. SIMPLIFIED BLOCK DIAGRAM OF THE RXMUTE FUNCTION ............................................................................................ 26

3.0 TRANSMIT PATH LINE INTERFACE ................................................................................................. 27

FIGURE 13. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT PATH................................................................................................... 27

3.1 TCLK/TPOS/TNEG DIGITAL INPUTS ............................................................................................................ 27

FIGURE 14. TRANSMIT DATA SAMPLED ON FALLING EDGE OF TCLK ............................................................................................... 27

FIGURE 15. TRANSMIT DATA SAMPLED ON RISING EDGE OF TCLK ................................................................................................. 27

TABLE 5: TIMING SPECIFICATIONS FOR TCLK/TPOS/TNEG ........................................................................................................... 28

3.2 HDB3 ENCODER ............................................................................................................................................ 28

TABLE 6: EXAMPLES OF HDB3 ENCODING...................................................................................................................................... 28

3.3 TRANSMIT JITTER ATTENUATOR ............................................................................................................... 29

TABLE 7: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS .................................................................................... 29

3.4 TAOS (TRANSMIT ALL ONES) ..................................................................................................................... 29

FIGURE 16. TAOS (TRANSMIT ALL ONES)...................................................................................................................................... 29

3.5 TRANSMIT DIAGNOSTIC FEATURES .......................................................................................................... 29

3.5.1 ATAOS (AUTOMATIC TRANSMIT ALL ONES)......................................................................................................... 29

FIGURE 17. SIMPLIFIED BLOCK DIAGRAM OF THE ATAOS FUNCTION............................................................................................... 30

3.5.2 QRSS GENERATION.................................................................................................................................................. 30

TABLE 8: RANDOM BIT SEQUENCE POLYNOMIALS ........................................................................................................................... 30

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