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EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
IN_
AUXIN, VCC
SDA,
SCL
(ADC MUX)
A0
ANALOG
BLOCK
DIGITAL
BLOCK
(ADC)
COMPARATORS
LOGIC NETWORK
FOR OUTPUTS
MR
MARGIN
(ADC REGISTERS)
WATCHDOG
TIMER
OUTPUT
STAGES
WDI,
RESET
RESET
UV/OV
WDO
SERIAL
INTERFACE
MAX6884
MAX6885
REGISTER BANK
BOOT
CONTROLLER
EEPROM
(USER AND CONFIG)
( ) MAX6884 ONLY
Figure 1. Top-Level Block Diagram
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