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MAX2022EVKIT

MAX2022 Evaluation Kit

Maxim Integrated 

MAX2022 Evaluation Kit

The desired sideband power level should be approxi-

mately -23.5dBm (-20.5dBm output power including

3dB pad loss). Phase and amplitude differences at the

I and Q inputs result in degradation of the sideband

suppression. Note that the spectrum analyzer’s uncali-

brated absolute magnitude accuracy is typically no

better than ±1dB.

Detailed Description

The MAX2022 is designed for upconverting (downcon-

verting) to (from) a 1500MHz to 2500MHz RF from (to)

baseband. Applications include single- and multicarrier

1800MHz to 2200MHz UMTS/WCDMA, cdma2000,

DCS/PCS, and WiMAX base stations. Direct upconver-

sion (downconversion) architectures are advantageous

since they significantly reduce transmitter (receiver)

cost, part count, and power consumption compared to

traditional heterodyne conversion systems.

The MAX2022 integrates internal baluns, an LO buffer,

a phase splitter, two LO driver amplifiers, two matched

double-balanced passive mixers, and a wideband

quadrature combiner. Precision matching between the

in-phase and quadrature channels, and highly linear

mixers achieve excellent dynamic range, ACLR, 1dB

compression point, along with LO and sideband sup-

pression, making it ideal for 4-carrier W-CDMA/UMTS

operation.

The MAX2022 EV kit circuit allows for thorough analysis

and a simple design-in.

Supply-Decoupling Capacitors

The MAX2022 has several RF processing stages that

use the various VCC pins. While they have on-chip

decoupling, off-chip interaction between them may

degrade gain, linearity, carrier suppression, and output

power. Proper voltage-supply bypassing is essential for

high-frequency circuit stability.

C1, C6, C7, C10, and C13 are 22pF supply-decoupling

capacitors used to filter high-frequency noise. C2, C5,

C8, C11, and C12 are larger 0.1µF capacitors used for

filtering lower-frequency noise on the supply.

DC-Blocking Capacitors

The MAX2022 has internal baluns at the RF output and

LO input. These inputs have almost 0Ω resistance at

DC, and so DC-blocking capacitors C3 and C9 are

used to prevent any external bias from being shunted

directly to ground.

LO Bias

The bias current for the integrated LO buffer is set with

resistor R1 (432Ω ±1%). Resistors R2 (562Ω ±1%) and

R3 (301Ω ±1%) set the bias currents for the LO driver

amplifiers. Increasing the value of R1, R2, and R3

reduces the current, but the device will operate at

reduced performance levels. Doubling the values of R1,

R2, and R3 reduces the total current to approximately

166mA, but the OIP3 degrades by approximately 4.5dB.

IF Bias

When desired, a common-mode voltage can be inject-

ed onto the BB input lines through TP3 on the EV kit. To

enable this feature, the proper value of resistors R5, R6,

R9, R10, and R12–R15 need to be installed. Resistors

R15/R14 and R13/R12 form voltage-dividers, while R5,

R6, R9, and R10 are large-value bias injection resistors.

See Figure 3 for EV kit schematic details.

External Diplexer

LO leakage at the RF port can be nulled to a level less

than -80dBm by introducing DC offsets at the I and Q

ports. However, this null at the RF port can be compro-

mised by an improperly terminated I/Q IF interface.

Care must be taken to match the I/Q ports to the driving

DAC circuitry. Without matching, the LO’s second-order

(2fLO) term may leak back into the modulator’s I/Q input

port where it can mix with the internal LO signal to pro-

duce additional LO leakage at the RF output. This leak-

age effectively counteracts against the LO nulling. In

addition, the LO signal reflected at the I/Q IF port pro-

duces a residual DC term that can disturb the nulling

condition.

As shown in Figure 1, providing an RC termination on

each of the I+, I-, Q+, Q- ports reduces the amount of

LO leakage present at the RF port under varying temp-

erature, LO frequency, and baseband drive conditions.

Note that the resistor value is chosen to be 100Ω with a

corner frequency 1 / (2πRC) selected to adequately filter

the fLO and 2fLO leakage, yet not affecting the flatness

of the baseband response at the highest baseband

frequency. The common-mode fLO and 2fLO signals at

I+/I- and Q+/Q- effectively see the RC networks and

thus become terminated in 50Ω (R/2). The RC network

provides a path for absorbing the 2fLO and fLO leakage,

while the inductor provides high impedance at fLO and

2fLO to help the diplexing process.

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