SL74LV14D Просмотр технического описания (PDF) - System Logic Semiconductor

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SL74LV14D

Hex Schmitt-Trigger Inverter

System Logic Semiconductor 

CHIP PAD DIAGRAM SL74LV14

1.33 ±0.03

13 12 11 10

09

14

01

02

03 04

08

07

05 06

Chip marking

IN74LV14

(x=0.130; y=0.130)

Pad size 0.108 x 0.108 mm (Pad size is given as per metallization layer)

Thickness of chip 0.46 ± 0,02 mm

PAD LOCATION

Pad No

01

02

03

04

05

06

07

08

09

10

11

12

13

14

Symbol

A1

Y1

A2

Y2

A3

Y3

GND

Y4

A4

Y5

A5

Y6

A6

VCC

X

0.130

0.130

0.381

0.616

0.881

1.116

1.115

1.115

1.115

0.804

0.569

0.378

0.143

0.130

SL74LV14

Y

0.463

0.230

0.126

0.126

0.126

0.126

0.631

0.846

1.181

1.194

1.194

1.194

1.194

0.813

SLS System Logic

Semiconductor

6

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