V58C265804S-6 Просмотр технического описания (PDF) - Mosel Vitelic, Corp

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V58C265804S-6

HIGH PERFORMANCE 2.5 VOLT 8M X 8 DDR SDRAM 4 BANKS X 2Mbit X 8

Mosel Vitelic, Corp 

MOSEL VITELIC

V58C265804S

Signal Pin Description

Pin

CLK

CLK

CKE

Type

Input

Input

CS

Input

RAS, CAS Input

WE

DQS

Input/

Output

A0 - A11 Input

Signal Polarity

Function

Pulse

Positive The system clock input. All inputs except DQs and DMs are sampled on the rising edge

Edge of CLK.

Level Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby

initiates either the Power Down mode, Suspend mode, or the Self Refresh mode.

Pulse

Active Low CS enables the command decoder when low and disables the command decoder when

high. When the command decoder is disabled, new commands are ignored but previous

operations continue.

Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the

command to be executed by the SDRAM.

Pulse

Active High Active on both edges for data input and output.

Center aligned to input data

Edge aligned to output data

Level

—

During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)

when sampled at the rising clock edge.

During a Read or Write command cycle, A0-An defines the column address (CA0-CAn)

when sampled at the rising clock edge.CAn depends from the SDRAM organization:

8M x 8 SDRAM CAn = CA8 (Page Length = 512 bits)

BA0,

BA1

DQx

DM

Input

Input/

Output

Input

VDD, VSS Supply

VDDQ Supply

VSSQ

VREF Input

Level

In addition to the column address, A10(=AP) is used to invoke autoprecharge operation

at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and

BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.

During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1

to control which bank(s) to precharge. If A10 is high, all four banks will be precharged

simultaneously regardless of state of BA0 and BA1.

—

Selects which bank is to be active.

Level

—

Data Input/Output pins operate in the same manner as on conventional DRAMs.

Pulse Active High In Write mode, DM has a latency of zero and operates as a word mask by allowing input

data to be written if it is low but blocks the write operation if is high.

Power and ground for the input buffers and the core logic.

—

—

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

Level

—

SSTL Reference Voltage for Inputs

V58C265804S Rev. 1.3 January 2000

4

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