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V58C265804SL-7

HIGH PERFORMANCE 2.5 VOLT 8M X 8 DDR SDRAM 4 BANKS X 2Mbit X 8

Mosel Vitelic, Corp 

MOSEL VITELIC

V58C265804S

Data Strobe Preamble and Postamble Timings for DDR Read Cycles

(CAS Latency = 2; Burst Length = 2)

T0

T1

T2

T3

T4

CK, CK

Command

DQS

DQ

READ

NOP

tRPRE(min)

NOP

NOP

tRPRE(max)

tRPST(min)

tDQSQ(min)

tRPST(max)

D0

D1

tDQSQ(max)

Consecutive Burst Read Operation and Effects on the Data Strobe Preamble and Postamble

Burst Read Operation (CAS Latency = 2; Burst Length = 4)

CK, CK

Command

DQS

DQ

ReadA

NOP

ReadB

NOP

NOP

NOP

NOP

NOP

D0A D1A D2A D3A D0B D1B D2B D3B

Burst Read Operation (CAS Latency = 2; Burst Length = 4)

CK, CK

Command

DQS

DQ

ReadA

NOP

NOP

ReadB

NOP

NOP

NOP

NOP

D0A D1A D2A D3A

D0B D1B D2B D3B

NOP

NOP

V58C265804S Rev. 1.3 January 2000

11

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