V58C3643204SAT-55 Просмотр технического описания (PDF) - Mosel Vitelic, Corp

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V58C3643204SAT-55

HIGH PERFORMANCE 3.3 VOLT 2M X 32 DDR SDRAM 4 X 512K X 32

Mosel Vitelic, Corp 

MOSEL VITELIC

Block Diagram

Column Addresses

A0 - A7, AP, BA0, BA1

Column address

counter

Column address

buffer

Row decoder

Memory array

Bank 0

512K x 32

Row decoder

Memory array

Bank 1

512K x 32

V58C3643204SAT

Row Addresses

A0 - A10, BA0, BA1

Row address

buffer

Refresh Counter

Row decoder

Memory array

Bank 2

512K x 32

Row decoder

Memory array

Bank 3

512K x 32

CLK, CLK

DQS

Input buffer Output buffer

DLL

Strobe

Gen.

DQ0-DQ

Data Strobe

Control logic & timing generator

V58C3643204SAT Rev. 1.4 August 2001

2

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