GF9101 Просмотр технического описания (PDF) - Unspecified

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производитель

GF9101

High Performance Multirate Digital Filter

Unspecified 

OFFSET [7..0]

8

FB–SEL-1

20

R1

FILTER–SUM 1

20

0

Σ

R2

1

20

R

GF9101

DEVICE No.1

20

FB–SEL-2

20

R3

FILTER–SUM 2

20

0 20

Σ 20

R4

1

20

12

OUTPUT [11..0]

R

GF9101

DEVICE No.2

Fig. 14 Pipelined Output Stages for Two Cascaded GF9101’s

TABLE 12: Internal RAM Address and Contents for a 48-tap Asymmetric Filter using Two Cascaded GF9101’s

COEF_ADDR

INTERNAL RAM CONTENTS

Device No. 1

Device No. 2

00H

C0 —> C11 (registers A1 —> A12)

C12 —> C23 (registers A1 —> A12)

01H

C47 —> C36 (registers B1 —> B12)

C35 —> C24 (registers B1 —> B12)

Dedicated serial PROM's can be used to load the

coefficients into the internal RAM of each GF9101. Note that

when data is fed back into DATA_B_IN, it enters register

B12 of device number 2. Therefore, while loading the

coefficients into the internal RAM for the B registers the

coefficients should be arranged as shown in Table 12. If a

single source is used for coefficient loading, the LOAD_EN

signal is used to select the appropriate device. Also, the

S_LOAD_CMP signal can be used as an indicator for a

successful load.

CLK_IN

DATA_A_IN

ENA

ENB

SEL_A/B

COEF_ADDR

(6-0)

LOAD_EN

ZERO

CONFIGURE

FB_SEL-1

FB_SEL-2

NEGATE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

00H

01H

00H

01H

00H

01H

00H

01H

00H

01H

00H

01H

00H

01H

Fig. 15 Timing Diagram for a 48 Tap Asymmetric Filter

15

520 - 64 - 7

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