GF9101 Просмотр технического описания (PDF) - Unspecified
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GF9101 Datasheet PDF : 23 Pages
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DATA_A_IN
0
1
2
CLK_IN
ENA
ENB
B
A
B
SEL_A/B
COEF_ADDR
(6-0)
01H
00H
01H
ENC
LOAD_EN
ZERO
CONFIGURE
3
4
5
6
A
B
A
B
00H
01H
00H
01H
7
8
9
10
A
B
A
B
00H
01H
00H
01H
FB _SEL
PIPELINE _OUT
Fig. 11 Timing Diagram for a 24 Tap Asymmetric Filter
DATA–A–IN
A23
A22
A21
A13
A12
DATA–B–OUT
A0
A1
A2
A10
A11
x
C0
x C1
x C2
x
C10
x C11
DATA–A–IN A23
A22
A21
A13
A12
DATA–B–OUT
A0
A1
A2
A10
A11
x
C23
x C22
x C21
x C13
x C12
Σ
PIPELINED
ADDER
Σ
PIPELINED
ADDER
(A23 x C0) + (A22 x C1) + (A21 x C2) +...+(A13 x C10) + (A12 x C11)
Fig. 11a Data Flow Diagram for a 24 Tap Asymmetric Filter
(A0 x C23) + (A1 x C22) + (A2 x C21) +...+(A10 x C13) + (A11 x C12)
+
(A23 x C0) + (A22 x C1) + (A21 x C2) +...+(A13 x C10) + (A12 x C11)
Fig. 11b Data Flow Diagram for a 24 Tap Asymmetric Filter
CASCADING
In the previous section, configuration for a 24 tap filter using
only one GF9101 was shown. To realize higher order (>24)
filters, up to three GF9101's would allow a 72 tap FIR filter to
be configured without any additional hardware. In Figure
13, two GF9101's are cascaded together to obtain a 48 tap
filter. The data enters DATA_A_IN (device number 1) and
exits from DATA_B_OUT (device number 1). In device
number 2, the DATA_A_OUT bus is connected to
DATA_B_IN in order to feed the data back in to the B12
register of the same device. The contents of the
configuration register will be different for the two devices to
compensate for a three register delay introduced when two
GF9101's are cascaded to get a 48 tap filter. The
configuration register contents are shown in Table 11.
12
520 - 64 - 7
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