MBM29PDS322BE Просмотр технического описания (PDF) - Fujitsu

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MBM29PDS322BE

32M (2M × 16) BIT Page Dual Operation

Fujitsu 

MBM29PDS322TE/BE 10/11

Table 4: MBM29PDS322TE/BE Command Definitions

Command

Sequence

Bus

Write

Cycles

Req’d

First Bus

Write Cycle

Addr. Data

Second Bus

Write Cycle

Addr. Data

Third Bus

Write Cycle

Addr. Data

Fourth Bus

Read/Write

Cycle

Addr. Data

Fifth Bus

Write Cycle

Addr. Data

Sixth Bus

Write Cycle

Addr. Data

Read/Reset Word 1 XXXh F0h — — — — — — — — — —

Read/Reset Word 3 555h AAh 2AAh 55h 555h F0h RA RD — — — —

Auto

select

Word 3

555h

AAh 2AAh

55h

(BA)

555h

90h

—

—

—

—

—

—

Program Word 4 555h AAh 2AAh 55h 555h A0h PA PD — — — —

Chip Erase Word 6 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h 555h 10h

Sector

Erase

Word 6 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h SA 30h

Erase Suspend

1

BA B0h — — — — — — — — — —

Erase Resume

1

BA 30h — — — — — — — — — —

Set to

Fast Mode

Word

3

555h AAh 2AAh 55h 555h 20h —

—

—

—

—

—

Fast

Program *1

Word

2

XXXh A0h PA PD

—

—

—

—

—

—

—

—

Reset from

Fast Mode *1

Word

2

BA

90h

XXXh

*4

F0h

—

—

—

—

—

—

—

—

Extended

Sector Group Word 4 XXXh 60h SPA 60h SPA 40h SPA SD — — — —

Protection *2

Query

Word 1

(BA)

55h

98h

—

—

—

—

—

—

—

—

—

—

Hi-ROM

Entry

Word 3 555h AAh 2AAh 55h 555h 88h — — — — — —

Hi-ROM

Program *3

Word

4

555h

AAh 2AAh

55h

555h

A0h

(HRA)

PA

PD

—

—

—

—

Hi-ROM

Erase *3

Word 6 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h HRA 30h

Hi-ROM

Exit *3

Word 4

555h

AAh

2AAh

55h

(HRBA)

555h

90h

XXXh

00h

—

—

—

—

*1: This command is valid while Fast Mode.

*2: This command is valid while RESET = VID.

*3: This command is valid while Hi-ROM mode.

*4: The data “00h” is also acceptable.

Note

1.Address bits A20 to A12 = X = “H” or “L” for all address commands except or Program Address (PA), Sector

Address (SA), and Bank Address (BA).

2.Bus operations are defined in Table 8.

3.RA = Address of the memory location to be read

PA = Address of the memory location to be programmed

Addresses are latched on the falling edge of the write pulse.

9

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