FX641 Просмотр технического описания (PDF) - CML Microsystems Plc
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FX641 Datasheet PDF : 13 Pages
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Specification ......
Characteristics
See Note
Min.
Typ.
Max.
Unit
Channel Outputs (Ch1 and Ch2) Figure 5
Mode Change Time
Tone Follower Mode (Table 3)
Response and De-Response Time
Packet Mode (Table 3)
Response and De-Response Time
6
3, 4, 7
3, 4, 7
-
-
500
ns
-
-
10.0
ms
40.0
-
48.0
ms
Notes
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
Tone Follower or Packet mode enabled; see Table 3.
Tristate selected; see Table 3.
With adherence to Signal-to-Voice and Signal-to Noise specifications.
12kHz and/or 16kHz system.
With Input Amp gain setting = 0dB.
Time taken to change between any two of the operational modes: Tone Follower, Packet or Tristate, and with
a maximum capacitive load of 30pF on an output.
The time delay, after a valid serial data load (or after device powerup), before the condition of the outputs can
be guaranteed correct.
Immunity to false responses and/or de-responses.
Common Mode SPM and balanced voice input signal.
With SPM and voice signal amplitudes balanced; to avoid false de-responses due to saturation, the peak-to-
peak voice + noise level at the output of the Input Amp should be no greater than the dynamic range of the
device. For this reason, the signal-to-voice figure at the Am[ Output will vary with the sensitivity setting. The
lowest signal-to-voice figure occurs at the highest sensitivity setting (Table 2, 27dB).
Maximum voice frequencies = 3.4kHz.
With the Input Amplifier gain at 0dB and the Bandpass Filter gain set at 0dB (Table 2); subtract 1.0dB from this
specification for each extra single dB of Bandpass Filter gain programmed.
Alternatively, with the input components as recommended in Figure 2, the sensitivity is as defined in Table 2.
Logic inputs with no internal pullup; Chip Select, Serial Data, Serial Clock, Output Enable, Output Select and
Clock In pins.
Logic inputs with an internal pullup; Preset Level and System Select pins.
Preset Level= ‘0’, System Select = don't care; Chip Select, Serial Clock and Serial Data inputs active;
see Table 3.
Preset Level = ‘1’, System Select = input active; Chip Select, Serial Clock and Serial Data inputs inactive;
see Table 3.
CHIP SELECT
t CSE
t CYC
SERIAL CLOCK
SERIAL DATA
tDS
tDH
tPWL
tPWH
BIT D5
Don’t
Care
Data
BIT D4
D3
Fig.9 Data Load Timing for the Controlled Sensitivity Mode
Parameter
tPWH Serial Clock ‘High’ Pulse Width
tPWL Serial Clock ‘Low’ Pulse Width
tCYC Serial Clock Period
tCSE Chip Select ‘Low’ to Clock ‘High’ Edge
t
Data Hold Time
DH
tDS
Data Setup Time
tCSH Chip Select ‘High’ from:
Clock ‘High’ Edge
Clock ‘High’ Edge
Min.
250
250
600
450
50.0
250
50.0
-
Typ.
-
-
-
-
-
-
-
-
t CSH
BIT D0
Max.
-
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
-
ns
1
serial clock period
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