CS7666-KQ Просмотр технического описания (PDF) - Cirrus Logic

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CS7666-KQ

Digital Color-Space Processor for CCD Cameras

Cirrus Logic 

CS7666

Operational Control Register (06h)

7

6

res

ZV

Reserved

R/W

5

INTERL

R/W

4

INREF

R/W

3

2

1

0

OE

POSPIX

EBLU

OBLU

R/W

R/W

R/W

R/W

OBLU

EBLU

POSPIX

OE

Logic high causes the first line after VREF of the odd field to be processed as a BLUE line. Logic

low causes the first line of the odd field to be processed as a RED line.

Logic high causes the first line after VREF of the even field to be processed as a BLUE line.

Logic low causes the first line of the even field to be processed as a RED line.

Logic “1” causes the first pixel of the first line to be treated as a positive pixel in the color sep-

aration block. Logic “0” causes the first pixel to be treated as a negative pixel. Try toggling this

bit if the colors appear “reversed”.

The Output Enable Bit operates in conjunction with the external Output Enable Pin, as illustrat-

ed in Table 15.

INREF

INTERL

ZV A

OE Bit

0

0

1

1

OE Pin

0

1

0

1

Digital

Outputs

Enabled

High-Z

High-Z

Enabled

Table 15. OE Pin and Bit Operation

Logic “1” causes CS7666 to accept HREF input and VREF input pins as the reference inputs

signals. EAV and SAV codes in the CCD data stream are ignored. Logic “0” causes the internal

de-formatter to decode and follow the embedded EAV and SAV codes sent from the CCD dig-

itizer (as with the CS7615).

Logic “0” places the digital outputs in interleaved mode with alternate Y and CrCb data on the

DO[A0..A9] 10-Bit output. Logic “1” places the digital outputs in parallel mode with Y data on

DO[A0..A9] and CrCb on the DO[B0..B9] outputs.

Logic “1” causes VREFOUT pin to output a VSYNC signal compatible with ZV port specifica-

tions as well as many composite video encoders.

DS302PP1

23

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