CS7666-KQ Просмотр технического описания (PDF) - Cirrus Logic
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CS7666-KQ Datasheet PDF : 42 Pages
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CS7666
In 20-bit wide mode, the luminance information is
output on DOA[9:0] and the chrominance informa-
tion is output on DOB[9:0].
DOA[9:0]
DOB[9:0]
CLKOUT
Parallel
INTERL = 1
10-Bit
Luminance Data
10-Bit
Chrominance Data
Pixel Rate
Interleaved
INTERL = 0
Interleaved 10-Bit
Luminance Data
and 10-Bit
Chrominance Data
0
2x Pixel Rate
Table 5. INTERL Controlled Output Formats
The CS7666 supports both 8-bit and 10-bit opera-
tion as per the ITU-656 recommendation. The ITU-
656 recommendation defines the primary data path
as 8-bits wide with two additional fractional bits
that can be used to form a 10-bit data path. If only
8-bits of output data are used, the two LSBs, DOA1
and DOA0 (DOB1, DOB0) are not used. However,
DOA[9:2] (DOB[9:2]) are connected exactly the
same as in a 10-bit system. This is essential to
properly pass the image data and synchronization
signals to the next component.
Internal Horizontal Scaler
The internal horizontal scaler is used to bridge be-
tween common CCD imager formats and computer
or television formats. In the CS7665 compatibility
mode (default after reset) a 4:5 data rate scaler is
selected by setting the INTERP pin (pin 54 on the
CS7666) to a logical one. The 4:5 scaler will con-
vert a standard 512 horizontal pixel width CCD im-
ager used for cam-corders into the VGA 640x480
format. The CS7615 (if that device is used in the
system) must also have its INTERP pin set high.
Register 04h Pin 54 Operation Scaling Ratio
bit 4
0
0 CS7665 mode
1:1
0
1 CS7665 mode
4:5
1
X CS7666 mode programmable
Table 6. INTERP Pin (Pin 54)
When the CS7666 is in the native CS7666 mode
(True_7666 in register 04h set to 1), the INTERP
pin is ignored and the internal scaling ratio is pro-
grammed by the user. The CS7615 must have its
INTERP pin tied to ground.
Several pre-defined scaler modes may be selected
by writing a 3-bit value to bits 0-2 of register 04h.
These default scaling modes are described in
Table 7. If the CUSTOM bit (bit 3 of register 04h)
is set to a 1, then the scaling ratio is determined by
the M and N values contained in the Scaler Control
registers (2Dh - 2Fh.)
CLKIN and CLKIN2X Input Timing
The CLKIN, pin 55, will always require a primary
pixel rate clock source. CCD manufacturers gener-
ally specify a pixel clock frequency that is compat-
Mode
000
001
010
011
100
101
110
111
CCD Format
CCD
512x480
512x480
512x576
362x480
362x480
362x576
512x576
512x480
512x576
CCD Clock (MHz)
½ input clock
9.818
9.346
9.281
6.75
6.75
6.75
9.563
9.000
9.000
Output Format
same as CCD
640x480
720x480
720x480
640x480
720x480
720x576
720x576
720x480
720x576
Input Clock (MHz)
(30 MHz max.)
24.5454
27.000
27.000
24.5454
27.000
27.000
27.000
27.000
27.000
Table 7. Default Scaling Modes (Register 04h)
Scaling Ratio
1:1
4:5
9:13
11:16
11:20
1:2
17:24
2:3
14
DS302PP1
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