CS7615-KQ Просмотр технического описания (PDF) - Cirrus Logic
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CS7615-KQ Datasheet PDF : 36 Pages
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CS7615
REGISTER DESCRIPTIONS
Software Reset Register (00h)
7
6
5
4
3
2
1
0
res
res
res
SR4
res
res
res
res
r
r
r
w
r
r
r
r
SR4
Setting bit SR4 to logic high will initiate a CS7615 software reset. Software reset resets all the
digital blocks except for I2C and the ADC calibration logic. The clocks remain running. This reset
bit automatically clears.
Low Power Register (20h)
7
6
5
4
3
2
1
0
res
res
res
PD4
res
res
res
res
r
r
r
r/w
r
r
r
r
PD4
Setting bit PD4 to logic high will place the CS7615 chip in a low power mode. The I2C interface
and clock generation circuitry will remain powered up.
Operational control #1 Register (24h)
7
6
5
4
3
2
1
0
PAL
AGCW1
AGCW2
AGCDIS
AGCCALG
CCDTYP
FLCKLS
PALENV
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
PAL
AGCW
AGCDI
AGCALG
CCDTYP
FLCKLS
PALENV
R/W
R
W
RES
Logic high indicates a PAL standard camera system, logic low indicates NTSC. Default = 0.
Used to window the portion of the frame to use for AGC. Default = 00.
00 = use entire frame
01 = use center 1/4 area of frame
10 = use center 1/16 area of frame
11 = reserved
Logic high disables CS7615’s automatic gain control circuitry. User may manually control gain
through the gain register 25h/26h. Default = 0.
Controls data used in CS7615’s AGC loop. Logic high indicates mosaic data, logic low indicates
luma data. Default = 0.
Logic high signifies that a Type B CCD is being used, logic low signifies a Type A CCD. Default
= 0.
Logic high restricts shutter to flickerless settings. Default = 0.
Logic high when the camera system is being used in a PAL environment, logic low in an NTSC
environment. Default = 0.
Read/Write
Read
Write
Reserved
DS231PP6
17
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