![](/html/Intersil/822317/page7.png)
HSP45256/883
Timing Waveforms
CLK
tCP
tCH
tCL
DIN0-7
tDS tDH
tTS tTH
tTS
TXFR
tDO
DOUT0-7
CASOUT0-12,
AUXOUT0-8
FIGURE 1. INPUT, OUTPUT TIMING
CLOAD
A0-7
tCLH
t CLC
tAS tAH
DCONT0-7
tCS tCH
tCLL
FIGURE 2.
RLOAD
tRLL
A0-2
DREF0-7
tRLC
tAS tAH
tRS tRH
tRLH
FIGURE 3.
OEA, OEC
AUXOUT0-8
CASOUT0-12
DOUT0-7,
CASOUT0-12
AUXOUT0-8
tOD
tOE
1.7V
1.3V
tr, tf
2.0V
0.8V
FIGURE 4.
CLK
tTHCL
tCLLH
TXFR
RLOAD,
CLOAD
FIGURE 5. TRANSFER, LOAD TIMING WHEN BOTH OCCUR ON A SINGLE CYCLE
9-7