HSP45256883 Просмотр технического описания (PDF) - Intersil

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HSP45256883

Binary Correlator

Intersil 

HSP45256/883

TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS

Device Guaranteed and 100% Tested (Note 5)

PARAMETER

SYMBOL

(NOTE 5)

NOTES

GROUP A

SUB-

GROUPS

TEMPERATURE

(oC)

-25 (25.6MHz) -20 (20MHz)

MIN MAX MIN MAX UNITS

CLK Period

CLK High

CLK Low

CLOAD Cycle Time

CLOAD High

CLOAD Low

RLOAD Cycle Time

RLOAD High

RLOAD Low

Set-up Time; DIN to CLK

High

t CP

t CH

t CL

t CLC

t CLH

t CLL

t RLC

t RLH

t RLL

t DS

9, 10, 11

-55 ≤ TA ≤ 125

39

-

50

-

ns

9, 10, 11

-55 ≤ TA ≤ 125

15

-

20

-

ns

9, 10, 11

-55 ≤ TA ≤ 125

15

-

20

-

ns

9, 10, 11

-55 ≤ TA ≤ 125

39

-

50

-

ns

9, 10, 11

-55 ≤ TA ≤ 125

15

-

20

-

ns

9, 10, 11

-55 ≤ TA ≤ 125

15

-

20

-

ns

9, 10, 11

-55 ≤ TA ≤ 125

39

-

50

-

ns

9, 10, 11

-55 ≤ TA ≤ 125

15

-

20

-

ns

9, 10, 11

-55 ≤ TA ≤ 125

15

-

20

-

ns

9, 10, 11

-55 ≤ TA ≤ 125

13

-

15

-

ns

Hold Time; DIN to CLK

t DH

High

9, 10, 11

-55 ≤ TA ≤ 125

1

-

1

-

ns

Set-up Time; DREF to

t RS

RLOAD High

9, 10, 11

-55 ≤ TA ≤ 125

14

-

15

-

ns

Hold Time; DREF to

t RH

RLOAD High

9, 10, 11

-55 ≤ TA ≤ 125

1

-

1

-

ns

DCONT Set up Time

DCONT Hold Time

Address Set up Time

Address Hold Time

TXFR Set up Time

TXFR Hold Time

CLK to Output Delay

DOUT, AUXOUT,

CASOUT

t DCS

t DCH

t AS

t AH

t TS

t TH

t DO

9, 10, 11

9, 10, 11

9, 10, 11

9, 10, 11

9, 10, 11

9, 10, 11

9, 10, 11

-55 ≤ TA ≤ 125

-55 ≤ TA ≤ 125

-55 ≤ TA ≤ 125

-55 ≤ TA ≤ 125

-55 ≤ TA ≤ 125

-55 ≤ TA ≤ 125

-55 ≤ TA ≤ 125

13

-

15

-

ns

1

-

1

-

ns

13

-

15

-

ns

1

-

1

-

ns

13

-

15

-

ns

1

-

1

-

ns

-

20

-

25

ns

Output Enable Time

TXFR High to CLK Low

CLK Low to RLOAD,

CLOAD High

t OE

t THCL

t CLLH

Note 6

Note 7

Note 7

9, 10, 11

9, 10, 11

9, 10, 11

-55 ≤ TA ≤ 125

-55 ≤ TA ≤ 125

-55 ≤ TA ≤ 125

-

20

-

20

ns

3

-

4

-

ns

1

-

1

-

ns

NOTES:

5. AC testing is performed as follows: VCC = 4.5V and 5.5V. Input levels (CLK input) 4.0V and 0V; input levels (all other inputs) 3.0V and

0V; Timing reference levels (CLK) 2.0V; all others 1.5V. Output load per test load circuit with CL = 40pF. Output transition is measured

at VOH ≥ 1.5V and VOL ≤ 1.5V.

6. Transition is measured at ±200mV from steady state voltage, Output loading per test load circuit, CL = 40pF.

7. Applicable only when TXFR and RLOAD or CLOAD are active on the same cycle of CLK.

9-5

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