HSP45256883 Просмотр технического описания (PDF) - Intersil

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производитель

HSP45256883

Binary Correlator

Intersil 

HSP45256/883

Pin Description

SYMBOL

VCC

GND

DIN0-7

PIN NUMBER

D2, G9, K2

A10, B1, D10,

J10, L2

D1, E1-E3, F2,

F3, G1, G3

DOUT0-7

CLK

CASIN0-12

E9-E11, F9-F11,

G10, G11

C1

A1-A6, B2-B5,

C2, C5, C6

CASOUT0-12 A7-A9, A11,

B6-B11, C10,

C11, D11

OEC

C7

TXFR

L3

DREF0-7

F1, G2, H1, H2,

J1, J2, K1, L1

RLOAD K3

DCONT0-7 J6, J7, K6, K7,

L5-L8

CLOAD# K4

A0-2

J5, K5, L4

AUXOUT0-8 H10, H11, J11,

K9-K11, L9-L11

OEA

K8

Index Pin C3

TYPE

The +5V power supply pin.

Ground.

DESCRIPTION

I

The DIN0-7 bus consists of eight single data input pins. The assignment of the active

pins is determined by the configuration. Data is loaded synchronous to the rising edge

of CLK. DIN0 is the LSB.

O

The DOUT0-7 bus is the data output of the correlation array. The format of the output

is dependent on the window configuration and bit weighting. DOUT0 is the LSB.

I

System Clock. Positive edge triggered.

I

CASIN0-12 allows multiple correlators to be cascaded by connecting CASOUT0-12 of

one correlator to CASIN0-12 of another. The CASIN bus is added internally to the

correlation score to form CASOUT. CASIN0 is the LSB.

O

CASOUT0-12 is the output correlation score. This value is the delayed sum of all the

256 taps of one chip and CASIN0-12. When the part is configured to act as two

independent correlators, CASOUT0-8 represents the correlation score for the first

correlator while the second correlation score is available on the AUXOUT0-8 bus. In

this configuration, the cascading feature is no longer an option. CASOUT0 is the LSB.

I

OEC is the output enable for CASOUT0-12. When OEC is high, the output is three-stat-

ed. Processing is not interrupted by this pin (active low).

I

TXFR is a synchronous clock enable signal that allows the loading of the reference and

mask inputs from the preload register to the correlation array. Data is transferred on the

rising edge of CLK while TXFR is low (active low).

I

DREF0-7 is an 8-bit wide data reference input. This is the input data bus used to load

the reference data. RLOAD going active initiates the loading of the reference registers.

This input bus is used to load the reference registers of the correlation array. The man-

ner in which the reference data is loaded is determined by the window configuration. If

the window configuration is 1 x 256, the reference bits are loaded one at a time over

DREF7. When the HSP45256 is configured as an 8 x 32 array, the data is loaded into

all stages in parallel. In this case, DREF7 is the reference data for the first stage and

DREF0 is the reference data for the eighth stage. The contents of the reference data

registers are not affected by changing the window configuration. DREF0 is the LSB.

I

RLOAD enables loading of the reference registers. Data on DREF0-7 is loaded into the

preload registers on the rising edge of RLOAD. This data is transferred into the corre-

lation array by TXFR (active low).

I

DCONT0-7 is the control data input, which is used to load the mask bit for each tap as

well as the configuration registers. The mask data is sequentially loaded into the eight

stages in the same manner as the reference data. DCONT0 is the LSB.

I

CLOAD enables the loading of the data on DCONT0-7. The destination of this data is

controlled by A0-2 (active low).

I

A0-2 is a 3-bit address that determines what function will be performed when CLOAD

is active. This address bus is set up with respect to the rising edge of the load signal,

CLOAD. A0 is the LSB.

O

AUXOUT0-8 is a 9-bit bus that provides either the data reference output or the 9-bit

correlation score of the second correlator, depending on the configuration. When the

user programs the chip to be two separate correlators, the score of the second correla-

tor is output on this bus. When the user has programmed the chip to be one correlator,

AUXOUT0-7 represents the reference data out, with the state of AUXOUT0-8

undefined. AUXOUT0 is the LSB.

I

The OEA signal is the output enable for the AUXOUT0-8 output. When OEA is high, the

output is disabled. Processing is not interrupted by this pin (active low).

Used for orienting pin in socket or printed circuit board. Must be left as a no connect in

circuit.

9-3

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