ISPGDX80A-5Q208 Просмотр технического описания (PDF) - Lattice Semiconductor
Номер в каталоге
Компоненты Описание
производитель
ISPGDX80A-5Q208 Datasheet PDF : 25 Pages
| |||
Specifications ispGDX Family
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER #2
DESCRIPTION1
Inputs
tio
21 Input Buffer Delay
GRP
tgrp
22 GRP Delay
MUX
tmuxd
23 I/O Cell MUX A/B/C/D Data Delay
tmuxs
24 I/O Cell MUX A/B/C/D Data Select
Register
tiolat
25 I/O Latch Delay
tiosu
26 I/O Register Setup Time Before Clock
tioh
27 I/O Register Hold Time After Clock
tioco
28 I/O Register Clock to Output Delay
tior
29 I/O Reset to Output Delay
Data Path
trfdbk
30 I/O Register Feedback Delay
tiobp
31 I/O Register Bypass Delay
tioob
32 I/O Register Output Buffer Delay
tmuxc (Yx Clk) 33 I/O Register Data Input MUX Delay
tmuxc (I/O Clk) 34 I/O Register Data Input MUX Delay
tiod (Yx Clk) 35 I/O Register I/O Input MUX Delay
tiod (I/O Clk) 36 I/O Register I/O Input MUX Delay
Outputs
tob
37 Output Buffer Delay
tobs
38 Output Buffer Delay, Slow Slew
toen
39 I/O Cell OE to Output Enabled
toedis
40 I/O Cell OE to Output Disabled
tgoe
41 Global Output Enable Delay
ttoe
42 Test OE Enable Delay
Clocks
tcio
43 I/O Clock Delay
tgy0/1/2/3
44 Clock Delay, Y0/1/2/3
Global Reset
tgr
45 Global Reset to I/O Register/Latch
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to the Timing Model in this data sheet for further details.
-5
-7
MIN. MAX. MIN. MAX. UNITS
— 0.7 — 1.3 ns
— 2.0 — 2.5 ns
— 1.0 — 1.4 ns
— 2.5 — 3.4 ns
— 1.6 — 2.2 ns
— 1.6 — 1.8 ns
— 2.4 — 3.6 ns
— 1.6 — 2.2 ns
— 0.7 — 1.0 ns
— 0.2 — 0.3 ns
— 0.4 — 0.6 ns
— 0.1 — 0.7 ns
— 1.1 — 1.2 ns
— 2.1 — 3.2 ns
— 4.1 — 5.1 ns
— 5.1 — 7.1 ns
— 0.9 — 1.3 ns
— 5.9 — 8.3 ns
— 0.8 — 1.1 ns
— 0.8 — 1.1 ns
— 2.5 — 3.6 ns
— 8.2 — 10.9 ns
— 0.7 — 1.0 ns
— 2.4 — 2.8 ns
— 12.3 — 15.0 ns
9
Share Link: 