ISPGDX80A-7T100 Просмотр технического описания (PDF) - Lattice Semiconductor
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ISPGDX80A-7T100 Datasheet PDF : 25 Pages
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Specifications ispGDX Family
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST1
COND.
#
DESCRIPTION
tpd
A 1 Data Propagation Delay from any I/O pin to any I/O pin
tsel
A 2 Data Propagation Delay from MUXsel Inputs to any Output
fmax(ext)
tsu1
–
3
Clock Frequency with External Feedback
(
1
tsu2+tgco1
)
– 4 Input Latch or Register Setup Time before any Clk
tsu2
– 5 Output Latch or Register MUX Data Setup Time before any Clk
th
– 6 Latch or Register Hold Time after any Clk
tgco1
tgco2
tco1
A 7 Output Latch or Register Clk (from Yx) to Output Delay
A 8 Input Latch or Register Clk (from Yx) to Output Delay
A 9 Output Latch or Register Clk (from I/O pin) to Output Delay
tco2
A 10 Input Latch or Register Clock (from I/O pin) to Output Delay
ten
B 11 Input to Output Enable
tdis
C 12 Input to Output Disable
ttoeen
B 13 Test OE Output Enable
ttoedis
C 14 Test OE Output Disable
twh
– 15 Clock Pulse Duration, High
twl
– 16 Clock Pulse Duration, Low
trst
– 17 Register Reset Delay from RESET Low
trw
– 18 Reset pulse width
tsl
A 19 Output Delay Adder for Output Timings Using Slow Slew Rate
tsk
A 20 Output Skew (tgco1 across chip)
1. All timings measured with one output switching, fast output slew rate setting, except tsl.
-5
-7
UNITS
MIN. MAX. MIN. MAX.
– 5.0 – 7.0 ns
– 6.5 – 9.0 ns
111 – 80.0 – MHz
4.0 – 5.5 – ns
4.0 – 5.5 – ns
0.0 – 0.0 – ns
– 5 – 7.0 ns
– 8.5 – 11.0 ns
6.0
9.0 ns
– 9.5 – 13.0 ns
– 6.0 – 8.5 ns
– 6.0 – 8.5 ns
– 9.0 – 12.0 ns
– 9.0 – 12.0 ns
3.5 – 5.0 – ns
3.5 – 5.0 – ns
– 14.0 – 18.0 ns
10.0 – 14.0 – ns
– 5.0 – 7.0 ns
– 0.5 – 0.5 ns
ispGDX timings are specified with a GRP load (fanout) of
four I/O cells. The figure at right shows the Maximum ∆
GRP Delay with increased GRP loads. These deltas
apply to any signal path traversing the GRP (MUXA-D,
OE, CLK, MUXsel0-1). Global Clock signals, which do
not use the GRP, have no fanout delay adder.
Maximum ∆ GRP Delay vs. I/O Cell Fanout
10
8
6
4
2
0 4 10 20 30 40 50 60 70
I/O Cell Fanout
8
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